--------------------------------------------------------------------------------
-- Company:  TU-Dresden
-- Engineer: Jörg Schneider
--           jsch@ite.inf.tu-dresden.de
--
-- Create Date:   07/2006
-- Design Name:   counter_listing_1
-- Module Name:   counter_listing_3_tb.vhd
-- Project Name:  counter design for linux magazin
-- Target Device: Spartan-3
-- Tool versions: ISE Webpack 8.1 
-- Description:   8 Bit counter
-- 
-- VHDL Test Bench Created by ISE for module: counter_listing_1
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY counter_listing_3_tb_vhd IS
END counter_listing_3_tb_vhd;

ARCHITECTURE behavior OF counter_listing_3_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT counter_listing_1
	PORT(
		clk_50mhz : IN std_logic;
		reset : IN std_logic;          
		led : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_50mhz :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';

	--Outputs
	SIGNAL led :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: counter_listing_1 PORT MAP(
		clk_50mhz => clk_50mhz,
		reset => reset,
		led => led
	);

	RESET_GENERATOR: process
	begin
  		reset <= '1';	
		  wait for 100 ns;		
		  reset <= '0'; 
		  wait for 1 us;
		  wait;
	end process;

   CLK_GENERATOR: process
	begin
	  clk_50mhz <= '0';
		  wait for 20 ns;
		  clk_50mhz <= '1';
	  wait for 20 ns;
	end process;

END;