----------------------------------------------------------------------------------
-- Company:  TU-Dresden
-- Engineer: Jörg Schneider 
--           jsch@ite.inf.tu-dresden.de
-- 
-- Create Date:    07/2006 
-- Design Name:    counter
-- Module Name:    counter_listing_4 - Behavioral 
-- Project Name:   counter design for linux magazin
-- Target Devices: Spartan-3
-- Tool versions:  ISE Webpack 8.1
-- Description:    8 Bit counter
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter_listing_4 is
  port (clk_50mhz : in  std_logic;
        reset     : in  std_logic;
        led       : out std_logic_vector(7 downto 0));
end counter_listing_4;

architecture Behavioral of counter_listing_4 is
  signal sig_ctr   : std_logic_vector(7  downto 0) := "00000000"; 
  signal delay_ctr : std_logic_vector(25 downto 0) := "00000000000000000000000000";
  signal clk       : std_logic;
  signal clk_div   : std_logic;
begin

  delay: process (clk_50mhz, reset)
  begin
    if (reset = '1') then
      delay_ctr<="00000000000000000000000000";
    elsif (clk_50mhz'event) and (clk_50mhz='1') then
      delay_ctr<=delay_ctr+"00000000000000000000000001";
	   
      if delay_ctr="00001011111010111100001000" then
        delay_ctr<="00000000000000000000000000";
	   clk_div <= '1';
	 else  
	   clk_div <= '0'; 
      end if;

    end if;
  end process delay;

  count : process (clk_div, reset)
  begin
    if (reset = '1') then
      sig_ctr<="11111111";
    elsif (clk_div'event) and (clk_div='1') then
      sig_ctr<= sig_ctr + 1;
    end if;
  end process count;

  led <= sig_ctr;
end Behavioral;