https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip [p] [logo2] [ ] [search] Welcome Log out Login Register [icon-twitt] [icon-faceb] [icon-rss] * ABOUT * BENCH * FORUMS * PODCAST [logo_resp] [ ] [search] ABOUT BENCH FORUMS PODCAST LOGIN REGISTER PC ComponentsV * CPUs * GPUs * Motherboards * SSDs * Cases/Cooling/PSUs * Memory * NAS * Storage Smartphones & tabletsV * Smartphones * Tablets * Huawei * HTC * Samsung * Google/Android * Microsoft * Apple * SoCs SystemsV * Notebook Reviews * Desktop Reviews * Mac Reviews * Ultrabooks ENTERPRISE & IT GUIDESV * Best CPUs * Best SSDs * Best Laptops * Best Android Phones * Best Video Cards * Best PSUs * Best Motherboards * Best Gaming Laptops * Best Mechanical Keyboards * Best Consumer HDDs DEALS * Home> CPUs [ ] Menu * PC ComponentsV + CPUs + GPUs + Motherboards + SSDs + Cases/Cooling/PSUs + Memory + NAS + Storage * Smartphones & tabletsV + Smartphones + Tablets + Huawei + HTC + Samsung + Google/Android + Microsoft + Apple + SoCs * SystemsV + Notebook Reviews + Desktop Reviews + Mac Reviews + Ultrabooks * Enterprise & IT * GuidesV + Best CPUs + Best SSDs + Best Laptops + Best Android Phones + Best Video Cards + Best PSUs + Best Motherboards + Best Gaming Laptops + Best Mechanical Keyboards + Best Consumer HDDs * Deals * TRENDING TOPICS * CPUs * Intel * GPUs * AMD * Storage * Motherboards * SSDs * Mobile * Smartphones * Home> * CPUs IBM Creates First 2nm Chip by Dr. Ian Cutress on May 6, 2021 6:00 AM EST * Posted in * CPUs * GPUs * SoCs * IBM * GAAFET * 2nm 57 Comments | Add A Comment 57 Comments + Add A Comment [IBM] Every decade is the decade that tests the limits of Moore's Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world's first 2 nanometer node chip. Names for Nodes Just to clarify here, while the process node is being called '2 nanometer', nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an 'equivalent 2D transistor' design. Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it's important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us. Transistor Density Today's announcement states that IBM's 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors. IBM states that the technology can fit '50 billion transistors onto a chip the size of a fingernail'. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM's press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM's transistor density at 333 million transistors per square millimeter (MTr/mm^2). For comparison: Peak Quoted Transistor Densities (MTr/mm2) AnandTech IBM TSMC Intel Samsung 22nm 16.50 16nm/14nm 28.88 44.67 33.32 10nm 52.51 100.76 51.82 7nm 91.20 237.18* 95.08 5nm 171.30 3nm 292.21* 2nm 333.33 Data from Wikichip, Different Fabs may have different counting methodologies * Estimated Logic Density As you can tell, different foundries have different official names with a variety of densities. It's worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling - often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns. [Row] Stacked GAA With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process. IBM's 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers. [S1_575px] Users might be wondering why we're hearing that IBM is the first to a 2nm chip. IBM is one of the world's leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain. [IBM] IBM Albany Research Center No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations. [IBM] Wafer up close The chip was designed and made at IBM's Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM's expansive patent and licensing portfolio for collaborations with partners. We have a set of questions with IBM's experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again. Related Reading * IBM and AMD to Advance Confidential Computing * Hot Chips 2020 Live Blog: IBM z15, a 5.2 GHz Mainframe CPU (11:00am PT) * IBM & Partners to Fight COVID-19 with Supercomputers, Forms COVID-19 HPC Consortium * Hot Chips 31 Live Blogs: IBM's Next Generation POWER * IBM to use Samsung 7nm EUV for Next-Gen POWER and z CPUs * IBM And Everspin Announce 19TB NVMe SSD With MRAM Write Cache * TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022 * Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm Tweet PRINT THIS ARTICLE * Post Your Comment [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] Please log in or sign up to comment. [ ] [Submit Comment] [ajax-loade] POST A COMMENT 57 Comments View All Comments * Matthias B V - Thursday, May 6, 2021 - link Really curious to see GAA in real appliction chips and if it is as massive of an improvement as it looks. Probably not for density but performance and power consumption. Also I am not sure if I got it right from Samsung but does it scale / perfroms especially better for SRAM than FinFET does? That would be a massive advantage! Reply * Hifihedgehog - Thursday, May 6, 2021 - link Exactly this. Display power generally dominates total system power consumption. Whoever wrote up that bio is trying too hard to create. Plus, IBM's stock has been receding since around 2012. So whenever they make some big promise about such and such, I take it with a boulder of salt. Making a one-off prototype is one thing. That happens sometimes as early as a decade in advance to real-world production! Actually delivering it consistently and competitively is a whole other matter entirely. The other big thing that has the alarm bells going off in my head for me right now is that their transistor density for 2nm is suspiciously close to TSMC's 3nm. I would not be surprised if Intel, through IBM, is trying to one up TSMC in perceived competitive edge who has used differing specifications to quote node size. And I would not be surprised if they are trying to reclaim their node leadership by stretching the truth a bit. Besides, TSMC's 3nm is already entering into production in 2022. When is IBM/Intel's 2nm even coming? If it's 2027, they might as well throw in the towel because TSMC will have already beat them to market with their comparable 3nm process by a good half a decade. Reply * Matthias B V - Thursday, May 6, 2021 - link Since IBM used to work with GF / SAMSUNG in the past and now also seems to collaborate more with Intel it would be interesting if / how this turns out for them taking on TSMC and if especially SAMSUNGs bet on GAA pays out... For me it looks like they didn't want to play catch up and just focused on 3nm GAA and less on 5nmLPE which is more of a 7nmLPU+. However if the numbers are right and the reduction of 50% for 3GAAE vs 7LPP is correct it would only be between TSMC 5 nm and TSMC3 nm but closer to their 5nm and similar to intels 7nm if you compare MTr/mm2 but maybe other factors are much better. Or they just take it safe and go more agressive with GAAP. Also curious if Intel can manage their 5nm GAA by 2024/25 and therefore catch up with TSMC GAA... Someone got insights on those? Reply * Alistair - Thursday, May 6, 2021 - link TSMC was not really that far ahead because of these differences in transistor densities, but now TSMC 5nm is close to where Intel is trying to get, but Intel is 3 years behind. Reply * Alistair - Thursday, May 6, 2021 - link 5nm is great, not surprised that Apple switched to Apple Silicon because of 5nm. Reply * Tams80 - Thursday, May 6, 2021 - link It does suggest that most of the advantage Apple have gained over the competition has merely been from buying up all of another company's capacity than from their own work. But hey, an advantage is an advantage! Reply * Otritus - Thursday, May 6, 2021 - link Apple's IPC lead is generations ahead of the competition, and even if they were on 7nm the power efficiency loss would not be enough to eliminate their performance and efficiency lead. Also, Apple heavily invests in TSMC's new nodes, allowing them to partake as essentially beta testers for new nodes, so they aren't "buying up all of another company's capacity than from their own work" when they are investing in and working with the other company to get their leading architectures to perform well while transitioning the node from a beta release to a full release. Reply * michael2k - Thursday, May 6, 2021 - link That's pretty false, especially if you read Anandtech: https://www.anandtech.com/show/16226/apple-silicon... A14, which is the basis for the M1, has 8 wide decode, and as per Anandtech: Featuring an 8-wide decode block, Apple's Firestorm is by far the current widest commercialized design in the industry. IBM's upcoming P10 Core in the POWER10 is the only other official design that's expected to come to market with such a wide decoder design, following Samsung's cancellation of their own M6 core which also was described as being design with such a wide design. Other contemporary designs such as AMD's Zen(1 through 3) and Intel's uarch's, x86 CPUs today still only feature a 4-wide decoder designs (Intel is 1+4) that is seemingly limited from going wider at this point in time due to the ISA's inherent variable instruction length nature, making designing decoders that are able to deal with aspect of the architecture more difficult compared to the ARM ISA's fixed-length instructions. Fundamentally Apple's HW has been 8 wide since 2019, 7 wide since 2017, and besides that, features a huge re-order buffer and execution units: A +-630 deep ROB is an immensely huge out-of-order window for Apple's new core, as it vastly outclasses any other design in the industry. Intel's Sunny Cove and Willow Cove cores are the second-most "deep" OOO designs out there with a 352 ROB structure, while AMD's newest Zen3 core makes due with 256 entries, and recent Arm designs such as the Cortex-X1 feature a 224 structure. On the Integer side, whose in-flight instructions and renaming physical register file capacity we estimate at around 354 entries, we find at least 7 execution ports for actual arithmetic operations. These include 4 simple ALUs capable of ADD instructions, 2 complex units which feature also MUL (multiply) capabilities, and what appears to be a dedicated integer division unit. On the floating point and vector execution side of things, the new Firestorm cores are actually more impressive as they a 33% increase in capabilities, enabled by Apple's addition of a fourth execution pipeline. The FP rename registers here seem to land at 384 entries, which is again comparatively massive. The four 128-bit NEON pipelines thus on paper match the current throughput capabilities of desktop cores from AMD and Intel, albeit with smaller vectors. Floating-point operations throughput here is 1:1 with the pipeline count, meaning Firestorm can do 4 FADDs and 4 FMULs per cycle with respectively 3 and 4 cycles latency. That's quadruple the per-cycle throughput of Intel CPUs and previous AMD CPUs, and still double that of the recent Zen3, of course, still running at lower frequency. So... process definitely means they can clock lower and consumer less power and pack more transistors in. However, even the 2018 A11 was fundamentally bigger in scope than AMD or Intel CPUs: https://www.anandtech.com/show/13392/the-iphone-xs... Monsoon (A11) and Vortex (A12) are extremely wide machines - with 6 integer execution pipelines among which two are complex units, two load/store units, two branch ports, and three FP/vector pipelines this gives an estimated 13 execution ports, far wider than Arm's upcoming Cortex A76 and also wider than Samsung's M3. In fact, assuming we're not looking at an atypical shared port situation, Apple's microarchitecture seems to far surpass anything else in terms of width, including desktop CPUs. Reply * kgardas - Thursday, May 6, 2021 - link Basically every feature you praise is transistor invasive which means 5nm for apple is a need and is a huge advantage for them. Anyway, tremont is amd64 platform implementation and provide 2x 3-wide decoder while Intel noted that this may be combined in custom design into 1x 6-wide decoder. So 4-wide (5-wide Intel except Tremont) is just current implementations limitations on this platform and IIRC some Intel engineers already noted that they have much wider designs already done. Reply * michael2k - Thursday, May 6, 2021 - link Apple already had an 8 wide in 2019 with the A13 at 7nm: Apple's microarchitecture being 8-wide actually isn't new to the new A14. I had gone back to the A13 and it seems I had made a mistake in the tests as I had originally deemed it a 7-wide machine. Re-testing it recently, I confirmed that it was in that generation that Apple had upgraded from a 7-wide decode which had been present in the A11 and 12. The big changes between A13 and A14 are additional 70 ROB and a 4th FP pipeline. So their 7nm process didn't give them any advantage over Intel's 10nm process (from this article 7nm TSMC only has a 91 MTr/mm2, vs 10nm Intel at 100 MTr/mm2), which means all performance can be attributed to Apple's 8 wide decode vs Intels' 4+1 wide decode, Apple's 560 ROB vs Intel's 352 ROB, Apple's 6 Int and 3 FP pipelines vs Intels combined 10 Int and FP pipelines (best as I can tell from Anandtech's 2019 Ice Lake review) https://www.anandtech.com/show/14514/examining-int... So... no, not unless you're arguing increasing the ROB from 560 to 630 and adding a 4th FP pipeline are transistor intensive. Reply * 1 * 2 * 3 * 4 * 5 * 6 * > PIPELINE STORIES + Submit News AT Deals: Western Digital 4TB Blue SATA SSD $339 at Amazon [dell_revea] IBM Creates First 2nm Chip AT Deals: Dell S2421HN 24-Inch FHD IPS Monitor Just $99 * GlobalFoundries Upgrades for Silicon Photonics in Quantum Computers * AT Deals: Seasonic 750-Watt FOCUS PX PSU $119 After Rebate * Intel EMEA To Partners: Not Invulnerable to Substrate Shortages through 2021 * Intel's Chief Revenue Officer: We have Silicon, but Shortages in Wi-Fi, Substrates, Panels * AT Deals: AMD Ryzen 7 3700X Drops To $304 * Intel to Invest $3.5 Billion USD into Foveros and EMIB Production in Rio Rancho * AT Deals: Logitech G503 Lightspeed Wireless Mouse Only $103 * NVIDIA Updates GeForce RTX 3060 Ethereum Throttle; Updated Drivers Required For Future 3060s * Best Android Phones: April 2021 TWEETS [twiiter_bi] * IanCutress: RT @markhachman: Which has the worst product names? * RyanSmithAT: After making their initial inroads with the Ryzen-powered Surface Laptop 3 in 2019, AMD and Microsoft's collaborati... https://t.co/VOjzhCIl7H * IanCutress: @Redfire753690 ICube4 looks like one of TSMC's base offerings tbh. Right now I believe TSMC has the wider portfoli... https://t.co/4RnE22UR09 * IanCutress: @Guy1ncogn1t0 It's a good thing most places let you order in wafers, not individual transistors * IanCutress: There's a lot Moore room than you might think. '2nm' might just be a name, but it's just the start. special: IB... https://t.co/MOOLwH7pq8 * RyanSmithAT: @Dachsjaeger Complicating all of this is that, although we haven't reached photorealistic rendering, in many respec... https://t.co/UDRiRDbjKv * RyanSmithAT: @Dachsjaeger Turing did amazingly well given the manufacturing constraints. But consumers paid handsomely for it. I... https://t.co/ijUooRB8Le * IanCutress: @usmanpirzada @lasserith @rogoway @PGelsinger That's pretty much what I thought. * RyanSmithAT: @Dachsjaeger And to be sure, RT is still totally worth it in the long run. But that doesn't change the fact that a... https://t.co/8OkaoVE6x2 * RyanSmithAT: @Dachsjaeger In fairness, that was well before we hit the GPU equivalent of Panamax. GPU performance was still rapi... https://t.co/7D5lMJQvk0 * andreif7: @TheKanter @_msw_ @jonmasters m5, 24-core Cascade. * andreif7: @apellegr Do you reckon there will be a v9 software package shift that solves all of this? * andreif7: @Thracks Sony is bottom tier amongst the mobile vendors when it comes to camera processing, you shouldn't expect mi... https://t.co/FrUQOh65Lt * andreif7: @aschilling @IanCutress @TheKanter I made that cutout with a bit of processing from one of their high res wafer shots. * andreif7: @Thracks You should avoid it if you care about battery life or camera quality. * ganeshts: @bdmurdock Not aware of a standard way, but I have seen simulator wrapper scripts with a `timeout' prefix. Also o... https: //t.co/aIgUTOeXcx * ganeshts: @mikeev @BrettHowse @IanCutress For games, a combination of Powershell + (WinAppDriver / AutoHotKey) works, but it... https://t.co/Fhh8j0VZLa * ganeshts: @mikeev @BrettHowse @IanCutress I use Perl & Python on RHEL for my primary work, and Powershell for all AnandTech-r... https://t.co/7uCllPz9T3 * ganeshts: @mikeev @BrettHowse @IanCutress As a generic scripting language, Powershell may not have any benefit over Perl or P... https://t.co/ttTIO97vrW * ganeshts: @owentparsons @karolgrudzinski @anandtech The LAN port on the far right is a 2.5Gbps one. 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