[HN Gopher] Die analysis of the 8087 math coprocessor's fast bit...
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       Die analysis of the 8087 math coprocessor's fast bit shifter
        
       Author : matt_d
       Score  : 82 points
       Date   : 2020-05-30 17:08 UTC (5 hours ago)
        
 (HTM) web link (www.righto.com)
 (TXT) w3m dump (www.righto.com)
        
       | Gracana wrote:
       | > So far, the bit and byte shifters only shift bits in one
       | direction. However, bits need to be shifted in both directions.
       | One of the key innovations of the 8087's shifter is its
       | bidirectional design: data can be passed through the shifter in
       | reverse to shift bits the opposite direction. This is possible
       | because the shifter is constructed with pass transistors, not
       | logic gates.
       | 
       | That's really cool. I've never really looked at ASIC design so
       | that wasn't something I had considered before. I have a left-
       | shift unit design that uses 74F logic, and to get it to do right
       | shifts I would have to reverse the input and output, which is the
       | typical trick to use when you have to use logic gates.
       | 
       | http://www.pnnk.org/img/lshift_schematic.pdf
       | 
       | http://www.pnnk.org/img/lshift_board.png
        
         | a1369209993 wrote:
         | Another approach you might try is to start with a rotator, then
         | mask off the leading or trailing bits for right or left shifts.
         | (Rotate right by X is the same as rotate left by N-X.)
        
         | beefok wrote:
         | I have always been fascinated by a paper on barrel shifters
         | myself. I think you would enjoy this as well:
         | https://www.princeton.edu/~rblee/ELE572Papers/Fall04Readings...
         | In particular, logarithmic barrel shifters are amazingly simple
         | to implement better than a massive multiplexer for each shift
         | step.
         | 
         | Edit: oops, after further investigation it looks like you may
         | be doing this in your design?
        
           | Gracana wrote:
           | Oh, nice paper! I had been looking at this one, also by
           | Matthew Pillmeier: https://preserve.lehigh.edu/cgi/viewconten
           | t.cgi?article=1714...
           | 
           | I have a verilog module that implements the "Mux-Based Data
           | Reversal" design with overflow output. Yosys/nextpnr
           | synthesize it with a 102MHz timing estimate on the lattice
           | ice40hx8k.
           | 
           | As for the 74F design, yeah, it uses the logarithmic
           | approach. It still has massive multiplexers, but there's only
           | 5 stages for a full 32 bit shift, plus the extra gates to
           | handle the carry bit.
        
             | beefok wrote:
             | Thank you so much, I'll ingest this into my system, haha.
             | Also, very cool results, that's really impressive! I'm a
             | computer engineer by trade (primarily FPGAs), so it's
             | always great to see other FPGA engineers (hi!). :)
        
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