[HN Gopher] How x86_64 Addresses Memory
___________________________________________________________________
How x86_64 Addresses Memory
Author : chmaynard
Score : 50 points
Date : 2020-06-13 20:24 UTC (2 hours ago)
(HTM) web link (blog.yossarian.net)
(TXT) w3m dump (blog.yossarian.net)
| esmi wrote:
| It's a nice tutorial on base plus index addressing but from the
| title I expected a tutorial on pointer tags as x86_64 is what
| makes tags even possible, i.e. we have a 64b address space but
| not 2^64 memory locations.
|
| https://www.mikeash.com/pyblog/friday-qa-2012-07-27-lets-bui...
|
| And for ARM.
|
| https://www.mikeash.com/pyblog/friday-qa-2013-09-27-arm64-an...
| saagarjha wrote:
| Actually, Objective-C's tagged pointers mostly rely on malloc's
| alignment guarantees.
| jart wrote:
| This is a good blog post about instruction encoding. I like to
| use this data structure to describe how memory addressing works
| in long mode: register char
| (*(*(*(*ram)[512])[512])[512])[4096] asm(cr3)
|
| Basically each modrm pointer thingy goes through four layers of
| page table indirection for each memory access, in order to turn
| virtual memory addresses into real memory addresses. But it's
| mostly an implementation detail where access to the above data
| structure is restricted to the operating system only,
| unfortunately, and the closest thing we have to using it is the
| mmap api.
| [deleted]
| stephc_int13 wrote:
| > mov rbx, 0xacabacabacabacab
|
| Am I the only one seeing this?
| danharaj wrote:
| all cats are beautiful
| chrisseaton wrote:
| > x86_64
|
| I don't know why people still use these crazy names. x86_64, x64,
| etc. The people who designed it call it AMD64. Let's call it
| that.
| jchw wrote:
| AMD64 and EM64T are actually not identical. Though it doesn't
| usually matter much in usermode, they are by specification not
| the same architecture. x86_64 is an umbrella for the various
| almost identical 64 bit extensions to x86.
| pm215 wrote:
| Unfortunately names get baked into things, so it's not as easy
| to change as just saying "let's change". "x86_64" is what Linux
| 'uname' and the gcc triplet naming conventions use, so that's
| what I go with, because it's the closest there is to a
| "standard" name in the software ecosystem I spend most time in.
| saagarjha wrote:
| x86_64 clearly shows it to be an extension of x86. The people
| designing things are not necessarily the people we should be
| listening to when consider what to call something, too;
| sometimes they're kind of bad at naming.
| monocasa wrote:
| It's only called x86_64 instead of amd64 because Intel was
| able to lobby the right people to not use AMD's name when
| implementing the standard AMD designed and published.
| saagarjha wrote:
| Sure, but I don't think the result was necessarily worse ;)
| [deleted]
| woodruffw wrote:
| Author here: I use AMD64 and x86_64 interchangeably (with a
| slight preference for the latter when publishing something,
| since it has more Google results than the former). I agree that
| the proliferation of names is an unfortunate mess.
|
| FWICT, "x64" is mostly limited to Microsoft. I wouldn't mind
| that one being thrown out.
| chrisseaton wrote:
| > FWICT, "x64" is mostly limited to Microsoft. I wouldn't
| mind that one being thrown out.
|
| Yes, that one particularly, since 86 and 64 don't even have
| anything to do with each other. One is a product number and
| the other is a word width - why did they replace one with the
| other?!
| jart wrote:
| Intel calls it IA-32e which I assume means Intel Architecture
| 32-bit w/ Extensions for 64-bit, 128-bit, 256-bit, and 512-bit
| computation. My preferred term for x86_64 is NexGen32e due how
| AMD bought NexGen which sold so much better than IA-64 that
| Intel ditched it and licensed the IP.
| to11mtm wrote:
| You left the DEC reference out of there.
|
| The K6 was a very competent chip but the you can see in the
| how the high level architecture starts to look much more like
| the EV6 with the Athlon series.
| chrisseaton wrote:
| I think they call it Intel 64. IA-32e is an execution mode,
| not an ISA.
|
| https://software.intel.com/content/www/us/en/develop/article.
| ..
| jeffbee wrote:
| Kinda weird that the author couldn't think of a use for
| base+index addressing. Doesn't it seem like the obvious
| application?
|
| Anyway, the tone of the article is unnecessary, IMHO. These
| addressing modes are useful and easy to understand, and the
| address generation units do double-duty as low-latency, high-
| throughput add-and-shift units, via the LEA instruction. CISC is
| useful, after all.
| userbinator wrote:
| _and the address generation units do double-duty as low-
| latency, high-throughput add-and-shift units, via the LEA
| instruction._
|
| For example, lea eax, [ecx+ecx*8+42]
|
| is equivalent to eax = ecx * 9 + 42, so you get a
| multiplication, an addition, and a move (without destroying the
| source register) in one instruction.
| woodruffw wrote:
| Author here: it's an extremely obvious application! 'saagarjha
| points out that I chastise myself later on for missing it while
| trying to contrive samples. I'll blame that one on writing this
| post in the middle of the night :-)
|
| With respect to the tone: it's a little flippant, sure. I work
| professionally on research programs that involve binary
| translating x86 (and other CISCs) into various representations
| for program analysis; what you're seeing is some of my
| frustration there bubble up.
| saagarjha wrote:
| > This is obvious in retrospect
|
| Otherwise smart people miss simple things all the time.
| Yushi212 wrote:
| To recover your lost Cryptocurrencies. Get in touch with DaTRek
| Recovery. Do a Google search to check them out. They are the best
| out there legit and can be trusted.
| danharaj wrote:
| Neat! I feel like wrapping my head around the 6502's indexed
| indirect addressing mode a few weeks ago well-prepared me for
| this article :)
___________________________________________________________________
(page generated 2020-06-13 23:00 UTC)