[HN Gopher] Inside the 8086 processor, tiny charge pumps create ...
___________________________________________________________________
Inside the 8086 processor, tiny charge pumps create a negative
voltage
Author : zdw
Score : 56 points
Date : 2020-07-25 16:58 UTC (6 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| binbag wrote:
| Nice article
| raphlinus wrote:
| Again, the number filter mangled the title. The full title from
| the article is "Inside the 8086 processor, tiny charge pumps
| create a negative voltage". In the interest of brevity,
| "processor" could be omitted or replaced with "chip."
| kens wrote:
| I was wondering why the title ended up so bizarre. In any case,
| I'm the author if anyone has questions on the 8086 internals.
| allenrb wrote:
| Hi Ken, love pretty much everything you write. Was wondering,
| is it correct to assume that all of the 8086 would have been
| laid out entirely by hand? Certainly special blocks like
| these charge pumps must have been, but was there any sort of
| design automation for things like the recently discussed
| register file?
| pjc50 wrote:
| Followup question: when did we start describing these
| things with GDSII files (was there a GDSI?) rather than
| giant sheets of acetate?
| kens wrote:
| I think it was a mixture of hand layout and automated
| layout. There are a lot of places that do strange things to
| squeeze out every last bit of space, and I think this
| optimization was done by machine.
|
| For instance, long signal traces have a lot of twists and
| turns to be as close together as possible while avoiding
| obstacles and satisfying the design rules. Sometimes these
| signals do strange things like switching from poly wires to
| metal wires and back just so they can be a bit closer.
| These micro-optimizations don't seem like ones a human
| would make.
|
| Another thing I've noticed is between two revisions of the
| chip that have identical layout except for a few traces. On
| one chip a trace will have a jog that's two 90-degree
| turns. On the other chip, the same trace will have 45
| degree bends. So the two traces are identical except for
| this short segment. I assume that the automated layout
| algorithm changed slightly, resulting in this change.
| userbinator wrote:
| _On one chip a trace will have a jog that 's two
| 90-degree turns. On the other chip, the same trace will
| have 45 degree bends._
|
| If the 45 degree one is the newer version, that might be
| a DFM optimisation - there is common folklore around PCB
| design that 90 or acute angles can cause various
| problems, with some hint of truth to it, but I suspect
| there are similar constraints in photolithography. If the
| sharp corner was causing yield losses, a newer revision
| would definitely address that.
| dboreham wrote:
| Electrons fly off as they try to take the 90 bend.
| amelius wrote:
| Electrons in a typical circuit have a drift velocity that
| is very low (order of millimeters per hour). Of course,
| the electrons individually are very fast, but they are
| also almost as fast when there is no voltage applied.
| userbinator wrote:
| There is a bit of truth to that --- sharp corners are
| more prone to electromigration:
|
| https://en.wikipedia.org/wiki/Electromigration#Via_arrang
| eme...
| kens wrote:
| Both chips have a mixture of 45 and 90 degree bends, so
| it's nothing that obvious. About 98% of the paths are the
| same and then there are these changes with no discernible
| pattern.
| egsmi wrote:
| In the suspected auto layout sections does it follow a
| modern standard cell convention?
| kens wrote:
| It's about as far as you can get from standard cell.
| Every logic gate is different with the transistors shaped
| to fit in their surroundings.
| nickff wrote:
| "Chip" is actually a term of art in the industry, used to
| describe 'single passives' (such as resistors and capacitors)
| in small SMD packages. There are machines called "chip
| shooters" which are designed to place those 'chips'.
|
| Using the term "chip" to describe integrated circuits is
| amateurish.
| kryptiskt wrote:
| Tell that to the IEEE https://www.hotchips.org
| dboreham wrote:
| Wrong.
| Treblemaker wrote:
| Perhaps so in the context of PCB assembly. In the
| semiconductor industry we still call them chips. So do Micron
| Semiconductor [1], TSMC [2] and Intel [3]
|
| [1] https://www.micron.com/foundation/semiconductors
|
| [2] https://www.tsmc.com/english/dedicatedFoundry/technology/
| SoI...
|
| [3] (pdf) http://download.intel.com/pressroom/kits/chipmaking
| /Making_o...
| pwg wrote:
| And the usage goes back to at least August 1975 (likely
| earlier):
|
| http://archive.6502.org/datasheets/mos_6501-6505_mpu_prelim
| i...
|
| "but including an _on-chip_ clock ... in addition to the
| _on-chip_ clock "
| dang wrote:
| Fixed now. Thanks!
| smitty1e wrote:
| > 3. Prototype designs always work.
|
| Looked jolly awesome on the whiteboard, though.
| userbinator wrote:
| Not only is the "back bias" "helpful", it is _necessary_ to
| prevent the transistors from conducting when they shouldn 't,
| which could lead to a latch-up and catastrophic failure; hence
| the power sequencing requirements of these ICs.
|
| (If you search online you'll find discussions such as
| https://electronics.stackexchange.com/questions/455745/why-w...
| where the accepted answer is close but not quite correct; -5 is
| substrate bias, 5 is the main supply, and 12 is applied to all
| the gates of the enhancement load transistors to open them. On
| the 8080, 12V was also used to drive the clocking circuitry, and
| this explains why the absolute maximum rating on all the pins ---
| and thus the gate oxide withstand voltage --- is 20V instead of
| the 6-7V typically seen for 5V devices.)
| egsmi wrote:
| Kens, I love the series on the 8086. For the next article can you
| go over how Intel did clock distribution?
| kens wrote:
| I was actually thinking about a short blog post on the 8086's
| clock circuit. The short answer is that the clock signal into
| the 8086 goes through a bunch of inverters to strengthen and
| shape the signal, and then two-phase clock signals (i.e. clock
| and clock') wind around the chip.
|
| Many processors of that era used pass transistors for temporary
| latches between circuits. The 8086 also used dynamic logic for
| gates, where instead of a pull-up resistor, the output would be
| precharged during one clock phase and then the gate would pull
| it down (or not) during the other clock phase.
___________________________________________________________________
(page generated 2020-07-25 23:00 UTC)