[HN Gopher] RISC-V: What's Missing and Who's Competing
       ___________________________________________________________________
        
       RISC-V: What's Missing and Who's Competing
        
       Author : SemiTom
       Score  : 37 points
       Date   : 2020-09-26 21:24 UTC (1 hours ago)
        
 (HTM) web link (semiengineering.com)
 (TXT) w3m dump (semiengineering.com)
        
       | TimSchumann wrote:
       | I actually just ordered a HiFive1 Rev B to play around with.
       | Kinda excited for the potential of RISC-V, we'll see how much
       | wind this article takes out of my sails. Thanks for sharing it.
        
       | 01100011 wrote:
       | Does anyone know how well RISC-V will be able to compete with ARM
       | in the higher end? It seems pretty easy to come up with a
       | processor design that is competitive in low-compute load
       | applications, but what about more advanced designs? I'm curious
       | what it is that ARM brings to the table there and if there is a
       | chance that RISC-V will ever offer serious competition.
       | 
       | Certainly RISC-V does not need to be the best to survive as a
       | viable option for most designs. It may absorb a lot of market
       | share from ARM in the long run. It will be interesting to see how
       | it develops.
        
         | TimSchumann wrote:
         | I'd say that depends on the higher end of what? Control over
         | the firmware, understanding of the actual bits you're flipping
         | and the architecture, power consumption, or raw computer per
         | clock?
        
           | mastazi wrote:
           | I'm not parent but personally I'm interested in performance
           | per Watt
        
       | ape4 wrote:
       | No integer overflow instruction I read on Hacker News the other
       | day.
        
       | azhenley wrote:
       | I've had a lot of fun learning RISC-V assembly off and on over
       | the last year. I went through a colleague of mine's tutorial
       | series on implementing an operating system targeting RISC-V using
       | Rust. Now I'm working on my own small assembler for RISC-V.
       | 
       | It's been so much more fun to learn than x86!
       | 
       | Edit: link to the tutorial (http://osblog.stephenmarz.com/)
        
         | faitswulff wrote:
         | Is this the tutorial you mentioned? EDIT - ah nevermind, turns
         | out there are at least two RISC-V OS tutorials in Rust:
         | 
         | -
         | https://gist.github.com/cb372/5f6bf16ca0682541260ae52fc11ea3...
         | 
         | - http://osblog.stephenmarz.com/
        
           | azhenley wrote:
           | The second one! Sorry, I meant to include it. I updated my
           | comment.
        
       ___________________________________________________________________
       (page generated 2020-09-26 23:00 UTC)