[HN Gopher] What is a System-on-Chip (SoC), and why do we care i...
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What is a System-on-Chip (SoC), and why do we care if they are open
source?
Author : parsecs
Score : 94 points
Date : 2020-11-09 19:45 UTC (3 hours ago)
(HTM) web link (www.bunniestudios.com)
(TXT) w3m dump (www.bunniestudios.com)
| kumarski wrote:
| efabless.com
|
| Open source chips are not common place right now, but maybe in
| like 10-15 years.
|
| Love bunniestudios posts.
| gentleman11 wrote:
| Librem is expensive and has less features than an android, but a
| lot of that cost went into more open hardware. It's not cheap to
| do that
| snvzz wrote:
| I don't think it's a good analogy.
|
| Librem uses a very proprietary, very closed SoC.
|
| The SoC has decent documentation, relative to the average of
| what passes for documentation these days, but that's about it.
| fsflover wrote:
| Is there any good source to read more about how closed it is?
| mulmen wrote:
| This open source chip is an FPGA with all the cost and speed
| limitations that carries. What would it take to create a truly
| open-source chip? I assume a chip fab can be contracted to build
| them given a workable design. Is this conceivable for a general
| purpose CPU? Will these FPGA approaches get us closer to such a
| goal?
| amock wrote:
| I don't know what the current status is, but I think
| https://hackaday.com/2020/06/30/your-own-open-source-asic-sk...
| is a good start on getting an open source fabricated.
| rektide wrote:
| As the other comments say, it's going to cost a million bucks
| probably to get something made. I wouldn't be shocked to hear
| numbers way lower for some smart folks. I wonder, for example,
| what it cost GreenArrays to get their chips made, how big their
| run was. But $1M i probably a pretty safe ballpark starting
| place.
|
| And we have pretty great open source cpu & ram design tools.
| MAGIC is free. There's a lot of great tools fora lot of this.
|
| What is not so great is all the un-core. And GPU, if you want
| that.
|
| The SiFive boards were coming with TileLink[1] as the main way
| to talk to the core, for a while, I believe, which is a pretty
| low level cache-coherent fabric used no where else. There's
| decent off the shelf to design a lot of the digital systems
| here. But I don't know what resources if any are available to
| help you build a chip-to-chip interface, to expose the
| TileLink. And there's basically the world's tiniest market for
| things to plug in on the other end anyways.
|
| When you buy an SoC, almost all embedded folk expect a bunch of
| semi-standard capabilities. I2C, I2S, DisplayPort, USB,
| Ethernet, &c are all common things you might want. While we can
| make a decent cpu now a days, afaik, we are still in very very
| very early days, very pre-implementation, for almost all of
| these. Thusfar almost everyone relies on buying closed IP to
| provide connectivity for the SoC they are making. It's quite
| likely to be the case as well for the new SiFive Unmatched
| board; I expect they bought someone's PCIe IP & integrated it.
|
| We are starting to see more neat work with FPGA implementations
| of various protocols like USB3 & PCIe but these all rely on the
| FPGA having really good transceivers that tackle the PHYsical
| layers, do the dirty work. Building actual transistors to be
| receivers & transmitters into & out of the chip, that's where,
| atm, we are all but babes, it feels like.
|
| [1] https://www.youtube.com/watch?v=EVITxp-SEp4
| mschuster91 wrote:
| > What would it take to create a truly open-source chip?
|
| From the article: 1M US-$ _at least_ for the masks plus a
| boatload of other upfront investment. If you 're for bleeding-
| edge tech like new fab processes, orders of magnitude more.
| mulmen wrote:
| Thanks I skimmed and missed that.
| snvzz wrote:
| >Will these FPGA approaches get us closer to such a goal?
|
| The same HDL that can be configured into an FPGA can be used to
| make chips.
|
| But we won't get there without the FPGA step. Chips aren't
| designed directly anymore. The sort of complexity we need these
| days means it's impossible to get right on the first try, and
| mistakes are very costly with ASICs.
| mschuster91 wrote:
| > The same HDL that can be configured into an FPGA can be
| used to make chips.
|
| Not exactly, you'll likely have to replace FPGA HW blocks for
| "hard IP" such as I/O (especially high speed interfaces such
| as HDMI/DP, MII, but also RAM controllers), power and clock
| management...
| iron2disulfide wrote:
| Of course "the same HDL" is a reductive statement, since
| components like high-speed IO, or even clock gates are not
| easily portable between FPGA vendors or foundries. But the
| user-land Verilog/VHDL code that describes how your custom
| thing "works" is generally portable.
| petra wrote:
| Let's compare this to QubesOS: Which adversary can hack QubesOS
| while not being able to hack this ?
| fsflover wrote:
| Intel: https://en.wikipedia.org/wiki/Intel_Management_Engine
| nullc wrote:
| If I have control of QuebesOS' ISP -- it's pretty easy to
| "hack" Qubes, sadly: There is pretty much no way to validate
| the qubes public keys, they're not signed by anything else. So
| the software can be substituted when you download it.
|
| More along the lines of what you're asking-- the virtualization
| creates a huge attack surface and there is a long history of VM
| escapes, microarch sidechannels, etc.
| fsflover wrote:
| Qubes OS does not use typical software virtualization
| methods. VT-d hardware virtualization it uses was broken only
| was, and it was done by the Qubes founder:
| https://en.wikipedia.org/wiki/Blue_Pill_(software)
| JBiserkov wrote:
| This is about the Precursor [0] to Betrusted [1].
|
| [0]: https://www.crowdsupply.com/sutajio-kosagi/precursor
|
| [1]: https://betrusted.io/
| ohazi wrote:
| Oh hey, I was just playing with this... it's really cool!
|
| There's a "Linux on LiteX-VexRiscv" design [1] that adds a DDR
| controller and MMU to the shared bus as well as a handful of
| other pieces that allow you to boot a Linux kernel image, mount a
| filesystem, and get a shell prompt over a serial terminal or ssh.
|
| You can then use familiar interfaces to talk to whatever
| peripherals you decided to include, e.g.: $
| echo 1 > /sys/class/gpio/gpio508/value $ echo 50 >
| /sys/class/pwm/pwmchip0/duty_cycle
|
| I got it to run on Greg Davill's [2] Orange Crab FPGA board [3]
| last night, which was actually pretty easy, as it's one of the
| supported boards. It was _surprisingly_ usable, even with the
| soft processor only running at 64 MHz. This was also the first
| time I used the open source synthesis / place-and-route tools to
| do anything more complicated than an adder, and they were _fast_
| and worked flawlessly.
|
| [1] https://github.com/litex-hub/linux-on-litex-vexriscv
|
| [2] https://twitter.com/gregdavill - He posts a lot of really
| cool macro and microscope photos of electronics assembly
|
| [3] https://github.com/gregdavill/OrangeCrab
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