[HN Gopher] Reverse-engineering the classic MK4116 16-kilobit DR...
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Reverse-engineering the classic MK4116 16-kilobit DRAM chip
Author : parsecs
Score : 55 points
Date : 2020-11-14 17:42 UTC (5 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| fred256 wrote:
| Reading about separate row and column addresses reminded me that
| the Apple II had its address lines arranged in such a way that
| the video circuitry would naturally read every row of memory,
| thus obviating the need for a separate refresh circuit.
|
| (To RAM, the order of address lines doesn't matter)
| jamwaffles wrote:
| I always get a bit excited when I see a righto.com post.
|
| An excellent read as usual.
| kens wrote:
| Thanks for your kind comment
| h2odragon wrote:
| At some level, all signals are analog. Lovely clever tricks every
| step of the way are necessary to make the nice abstract digital
| levels we try to think about. How might such tricks discriminate
| more states? can we have 3, 8, more state "bits"?
| mmastrac wrote:
| It just comes down to noise. If you can detect X levels
| successfully 1 out of 1x10^Y times, then you can ship it. Just
| set X and Y to whatever your specs should be.
| kens wrote:
| That's what flash memory does, it can store four bits per cell
| (quad-level-cell) https://en.wikipedia.org/wiki/Multi-
| level_cell
|
| The Intel 8087 math coprocessor stored two bits per transistor
| in its microcode ROM. It used four transistor sizes / voltage
| levels. This was necessary to fit the microcode on the die.
| https://www.righto.com/2018/09/two-bits-per-transistor-high-...
| cute_boi wrote:
| really love these reverse engineering articles <3
| kens wrote:
| Author here for all your vintage DRAM questions :-)
| djmips wrote:
| I'm so glad to see you tackle a DRAM since it's probably the
| one main component of a computer that is least understood since
| it is somewhat analog. Is dummy cell an official term? It's
| perfectly fine but I thought it might be better described as a
| reference cell. I enjoy seeing self correcting designs like
| this. My question would be - if you were to contrast to modern
| DRAM is it quite similar or what are the differences? (I saw
| your chart at the end but I'm guessing that there is more
| similar than different in a modern DRAM?)
| kens wrote:
| Dummy cell is the term used in the paper "Storage Array and
| Sense/Refresh Circuit for Single-Transistor Memory Cells"
| that introduced the idea. It's also the term used on the
| MK4116 datasheet and elsewhere.
|
| The capacitors in modern DRAMs are deep trenches, rather than
| a simple polysilicon plate. The trenches are 3.6 micrometers
| deep while the feature size is 45 nanometers, so they are
| remarkably deep. See the photos here:
| https://chipworksrealchips.blogspot.com/2014/02/intels-e-
| dra...
| phkahler wrote:
| Just wanted to say that is an amazing write up. My first
| computer was an Interact with 16K of memory built with these
| chips. I never knew how complex they really are until today. I
| knew the row/column multiplexing was a PITA for system
| designers, but was it really worth it? How much more did a
| package with 7 or 8 more pins cost back then? I guess that's x8
| for a system though.
|
| Anyway I hope someplace archives these documentary articles!
| kens wrote:
| I don't know how much more the larger packages cost, but it
| was enough that Intel really really didn't want to move off
| 16-pin packages, which caused problems for the 4004 and 8008
| processors. In addition, the larger packages took up more
| space on the circuit board which was a serious disadvantage,
| especially when you had a board full of memory chips.
| djmips wrote:
| From your new found knowledge of the 4116, do you have any
| insight into why the 4116 have a reputation for failure? They
| are often wholesale replaced with 4164 in old equipment.
| kens wrote:
| I don't know anything specific about 4116 reliability
| problems. But it makes sense that the 4164 would be a few
| years more modern and thus more reliable.
| drfuchs wrote:
| Great! Question: When 64K DRAM first appeared, I remember a
| cover article in EDN(?) claiming that nothing denser could ever
| be built, because cosmic radiation would zap individual
| electrons, and thus flip bits too frequently, and there was
| nothing you could do to protect from it. So, how was that
| thinking wrong?
| kens wrote:
| They discovered that most of the DRAM soft errors were due to
| alpha particles from the ceramic packaging. Changing the
| packaging solved most of the problem.
|
| There are still bit flips due to cosmic rays but the rate is
| low enough that most people don't care. ECC memory can be
| used if errors are a problem.
|
| More details on Wikipedia: https://en.wikipedia.org/wiki/Soft
| _error#Alpha_particles_fro...
| formerly_proven wrote:
| Some of Sun's servers famously suffered big reliability
| problems due to using IBM SRAM as caches, which is said to
| have had elevated error rates due to more alpha-emitting
| contaminants in their particular package filler.
| kens wrote:
| I was at Sun at the time (although not working on that),
| and these memory errors were a catastrophic problem for
| Sun. Customers were paying a lot of money for Sun's
| reliability and then systems started mysteriously having
| problems and Sun couldn't figure out why.
| musicale wrote:
| Nice. This is a really interesting design.
|
| I tend to like NMOS because of its compactness and simplicity
| (disadvantage is usually dissipating static power of course.)
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