[HN Gopher] Die Shots of the Raspberry Pi RP2040
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Die Shots of the Raspberry Pi RP2040
Author : mmastrac
Score : 204 points
Date : 2021-01-29 15:23 UTC (7 hours ago)
(HTM) web link (twitter.com)
(TXT) w3m dump (twitter.com)
| mmastrac wrote:
| Alternative Twitter thread:
| https://twitter.com/johndmcmaster/status/1355092011829719046
| jacquesm wrote:
| Yes, much better, thank you. (I made the same suggestion)
| dang wrote:
| Ok, we'll change to that from
| https://blog.adafruit.com/2021/01/29/die-shots-of-the-
| raspbe.... Thanks!
| breck wrote:
| Oh wow this thread (and his whole Twitter account) is gold.
| thanks for sharing.
|
| Edit: this zoomable image is great
| (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
| jacquesm wrote:
| Why not link to the original thread instead?
|
| https://twitter.com/johndmcmaster/status/1355092011829719046
| dang wrote:
| Changed from https://blog.adafruit.com/2021/01/29/die-shots-of-
| the-raspbe.... Thanks!
| AbraKdabra wrote:
| How does one of those die get made at all? It's such a minuscule
| small scale and it has such detail I cannot even comprehend how
| those components get "stamped" there, it's black magic.
| swalsh wrote:
| It's not really "Stamped". It's more of a photographic process.
| My basic understanding is that they apply a photographic
| reactive chemical, expose it. From there they apply another
| chemical process to form an oxidation layer, and then use an
| acid process to "etch" away material creating channels of
| positively charged particles. Then they can apply a mask, and
| throw tiny amounts of metal which will become the gate.
| geerlingguy wrote:
| The process of photolithography [1] involves a lot of complex
| optics, and interestingly you find a lot of lens
| manufacturers involved in it since it involves a lot of steps
| where light (e.g. lasers in this case) gets passed through a
| set of very precise optics until it hits the wafer and etches
| in the correct pattern from a larger 'reference copy'.
|
| [1] https://en.wikipedia.org/wiki/Photolithography
| baybal2 wrote:
| Actually, the process of actually "stamping" ICs mechanically
| is being pursued to make IC production even more cheaper.
|
| https://en.m.wikipedia.org/wiki/Nanoimprint_lithography
| kube-system wrote:
| Extremely simplified answer:
|
| You know how a microscope makes a small image really big? You
| can also do the same in reverse -- take a big picture and
| project it really small. Use that idea to project your design
| on to your silicon, coated in a series of photosensitive
| chemicals that etch away the silicon until you have what you
| want.
| acomjean wrote:
| From my partner who used to work at a fabless semiconductor:
|
| The chipmaking process starts with code. Veralog I think is
| still being used. https://en.wikipedia.org/wiki/Verilog
|
| You get information from your fab (libraries about sizes of
| things so you can do layouts and simulation with very expensive
| software (https://www.synopsys.com) (fun exercise, try to get a
| price on their website...)
|
| Often you send your design to the fab to get some samples to
| test back.
|
| Wikipedia has a decent summary about how the chips are made
|
| https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...
| pjc50 wrote:
| It is "just" photo-etching, with the big wrinkle that 40nm is
| way below the wavelength of light, so all sorts of clever
| tricks with diffraction have to be done to make it work.
| MarkusWandel wrote:
| A quick google for "homemade integrated circuit" brings up
|
| http://sam.zeloof.xyz/first-ic/
|
| At the very primitive end of the technology, integrated
| circuits can be made in the home workshop.
| auxym wrote:
| I like this animation showing how a FET is fabricated using
| photolithography processes:
| https://micro.magnet.fsu.edu/electromag/java/transistor/inde...
| blcArmadillo wrote:
| Thanks for sharing! It was really nice seeing each step of
| the process with a visualization.
| MuffinFlavored wrote:
| cheap microcontrollers:
|
| ESP32: WiFI, no USB
|
| RP2040: USB, no WiFi
|
| :(
| jesse_cureton wrote:
| The "Arduino Nano RP2040 Connect" is an RP4040 board slated to
| be coming soon that will provide WiFi and Bluetooth.
|
| I expect we'll see more RP2040 devboards & SOMs coming soon
| that fill the connectivity niche.
| 725686 wrote:
| The resistor value captcha at the end of the page is golden.
| war1025 wrote:
| How do I interact with it? I tried picking the colors, but
| nothing I tried did anything.
| allenu wrote:
| You can drag the slider. Clicking doesn't seem to work.
| war1025 wrote:
| Doesn't work for me on Firefox.
|
| I'm guessing it works on Chrome, but it also would sort of
| surprise me that a maker website wouldn't test against
| Firefox. Maybe I'm giving them too much credit.
| drewzero1 wrote:
| It took me a minute to figure out, you have to drag the
| circle up and down to select the number. I had expected
| to drag the whole bar - oops!
|
| Edit: Also on FF. (85.0 on Linux)
| allenu wrote:
| Strange. I'm on Firefox and it works for me.
| jsmith45 wrote:
| I'm suprised that even the CPU cores are implemented just as a
| sea of standard cells. It is common to have them be macros
| containing a clearly separate datapath and control logic.
|
| On the other hand, the fact that the prototyping was done on an
| FPGA makes this less surprising. Sea of cells is certainly easier
| to update, and less work than any form of manual datapath when
| migrating from FPGA to ASIC.
| mlyle wrote:
| Yup. This is pretty clearly a case of getting it to run on an
| FPGA and using a commercial FPGA to ASIC service instead of
| spending a lot of time in synthesis and validation.
|
| Mask costs can be cheaper this way, too, because some layers
| can be invariant between different parts.
| ohazi wrote:
| > using a commercial FPGA to ASIC service
|
| This was not an FPGA conversion.
|
| "Commercial FPGA to ASIC service" usually refers to
| Altera/Intel's HardCopy or Xilinx's EasyPath. EasyPath is
| where Xilinx sells you defective FPGAs for way cheaper, but
| with just enough of the right parts of the fabric working
| that your design can still fit and work properly. HardCopy is
| where Altera sells you a small number of metal mask layers to
| implement your design on a much smaller/faster sea-of-gates
| style ASIC that mimics the non-reprogrammable parts of the
| target FPGA.
|
| The Raspberry Pi Foundation did neither of these things. They
| _tested_ their design on an FPGA, which is common, and then
| used standard cell libraries and IP blocks provided by the
| fab and their partners to get through the _normal_ ASIC
| workflow.
|
| It turns out it's just easier and faster to tell the tools to
| automatically place and route the core complex than to do a
| careful floorplan. Also given that the RP2040 is apparently
| "very overclockable" (the PIO bitbanged HDMI output bumped
| the clock to something like double the nominally guaranteed
| maximum), the merits of doing it this way seem sound.
| 0xTJ wrote:
| Interestingly, there are documented bits in registers for
| marking whether you're running on an FPGA or as an ASIC.
| [deleted]
| myself248 wrote:
| How common is it to use copper bondwires? I thought these were
| always gold.
| samstave wrote:
| One of my regrets from when I worked at Intel was that we had die
| plans on 36x48 printouts in the lab - and they were beautiful, I
| wish I had taken them home - I would love to have some framed on
| my walls now.
| dboreham wrote:
| Interesting. I did not realize wire bonding is still used on
| large devices.
| tomcam wrote:
| Not a big fan of Twitter but I have to say it was an amazing use
| of the medium.
| mobilio wrote:
| Attention to detail is amazing!
| mbreese wrote:
| From the twitter thread, someone said it was fabbed by TSMC at
| 40nm.
|
| I wonder, with the cutting edge moving to smaller and smaller
| processes (5nm, etc)... how much of the older/larger capacity can
| be reused? Meaning, are we about to see a ton of cheaper chips
| like this RP2040 that are using older/slower/obsolete fab
| capacity? Or is the same equipment able to be used across a
| family of process sizes?
|
| In other words, once TSMC has X amount of capacity on 40nm, is
| that capacity always around and fixed to 40nm? If so, I imagine
| that creating new chips that don't need to be super fast will
| just become super cheap.
| baybal2 wrote:
| > how much of the older/larger capacity can be reused?
|
| Not only reused, but expanded, and improved over the years.
|
| So more than 100% of the original.
|
| The biggest surprise of the last few years was the growth in
| really, really old 200mm fab capacity (late eighties, early
| nineties tech.)
| lizknope wrote:
| The fab will eventually be upgraded. I design semiconductors
| and I have worked at two companies that had their own fabs (I
| didn't work in the fab)
|
| Back in 1997 the new technology was 0.25 micron (250nm) but we
| still operated fabs at 0.35, 0.6, 0.8, and 1 micron. I believe
| these 4 lines operated at 6 different factories.
|
| The next year we shut down the 1 micron fab. The building
| itself still had all the air filtering and cleanroom
| facilities. The old equipment (steppers, testers) was removed
| and new equipment for 0.18 micron was installed. I think this
| took about a year. At the end we still had 6 factories but the
| building that used to have all the old stuff was now the
| cutting edge fab.
| bobsmooth wrote:
| What happens to the old equipment? Scrap?
| peterburkimsher wrote:
| Usually the equipment is rented, and returned to the
| owners. I spent 4 years in Taiwan working for OSE, a
| semiconductor packaging company (cutting up silicon wafers,
| bonding wires onto them, and putting them into little
| plastic SD cards or RAM chips labelled "Made in Taiwan").
|
| The pick & place machines and ovens weren't owned by OSE -
| they were on a 30-year lease from other companies in Japan,
| Germany, etc.
|
| Software updates would void the warranty/lease conditions.
| One of my tasks was to write a program to measure yields
| for factory monitoring. This meant figuring out how to use
| SQL on Windows 2000, with no .NET framework or additional
| libraries.
|
| My guess is that when the equipment is too old, the
| original owners either take them back for salvaging, or
| sell off the pieces as scrap. I went to many scrapyards in
| Kaohsiung though, and found many treasures like $10
| bicycles or old consumer gadgets, but no factory-level
| machines.
| TorKlingberg wrote:
| Older processes available for cheap are not a new thing. They
| do indeed stay around until TSMC decide they're no longer worth
| running. It's not always cheaper as a larger process wastes
| more wafer.
| geerlingguy wrote:
| I believe Eben Upton mentioned in a Twitter thread somewhere
| that they were getting thousands of chips off each wafer at
| the current node size? Only had to order like 20 or 40 wafers
| for the first production run, something like that.
| avian wrote:
| Microelectronics cutting edge has been moving to smaller
| processes for the past 70 years. This is nothing new. If
| anything, the progress has slowed down.
|
| Some fabs get closed down/rebuilt for a different process, some
| stay and produce parts that don't benefit from higher
| densities. Last I checked some ICs still get produced in 0.35
| um processes. You don't need billions of transistors for an
| opamp.
| mlyle wrote:
| Microcontrollers being on larger processes like this is nothing
| new. As you mention, it's a way to keep using older fabs, but
| that's not the only reason.
|
| 40nm offers tons of performance for microcontrollers and the
| die area can still be reasonably small. You tend to want to
| have lots of variants of microcontrollers for different
| applications, so mask costs matter. And you tend not to want
| exotic, very low core voltages and _do_ want high voltage
| tolerances and strong drivers on the IOs, which mean relatively
| big geometry-- no matter what your minimum feature size is.
|
| Also, sleep power consumption is important, so low leakage is
| nice, which is easier to get on large geometry.
| baybal2 wrote:
| 40nm is a quite recent move for MCUs, and the mainstream
| majority can still be anywhere in between 90nm, and 180nm.
|
| Only very few, top of the line MCUs ventured to 40nm, like
| ESP32 which had no other option because of WiFi eating gates,
| or ST's MCUs with 3D accelerator on board.
|
| Problem for MCUs is that MCU specific features start to cost
| too much more in IP, design time, yields, and fab service
| cost below 90nm. Things like embedded flash, per-model mask
| memory, SRAM, non-CMOS cells, RF, and other analogue
| circuitry.
|
| Below 28nm conventional eFlash, and many other things stop
| scaling, and only proprietary solutions are on the table at
| the moment.
| petra wrote:
| BayBal, since you're an expert in Semi, I wonder if you can
| fill in the blanks?
|
| EbenUpton(Raspberry Pi's CEO) , on Twitter:"We get ~20k die
| per wafer""
|
| A Tsmc 40nm wafer costs about $2300.
|
| How much do you estimate the full chip manufacturing cost
| for this would be ?
|
| I wonder, because Eben Upton talked about "business model
| hacking" in regards to this chip, so they may want to do
| some interesting stuff in the mcu market.
| zeckalpha wrote:
| In the docs they described the naming convention for the
| processor, which suggests there are more under
| development
| swalsh wrote:
| For how long is the equipment for these fabs amortized?
| baybal2 wrote:
| All eternity really. Even eighties era equipment is still
| being bought, and resold. Quite a number of early nineties
| fabs still work producing pretty much same things for 30
| years straight.
| VectorLock wrote:
| Its easy to forget the long tail of smaller ICs these will
| get use out of for generations.
| monocasa wrote:
| Not long, around five years after full production.
| lmilcin wrote:
| This chip is very small and it does not benefit in any possible
| way from more advanced technological process. And using more
| advanced process means additional drawbacks and cost increases.
| teruakohatu wrote:
| I think it is safe to say they will come out with a WiFi
| version. The 40nm will be beneficial then.
| breck wrote:
| A simple stack of these images with a CSS offset (to give it a
| 3-d look) would be great.
|
| Edit: his zoomable image is even better
| (https://siliconpr0n.org/map/raspberry-pi/rp2-b0/mz_mit20x/#x...)
| rwmj wrote:
| How do you change the layer?
| teraflop wrote:
| If you navigate up one directory, there are a couple more
| layers available: https://siliconpr0n.org/map/raspberry-
| pi/rp2-b0/
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(page generated 2021-01-29 23:00 UTC)