[HN Gopher] SiFive P550 Core: High-Performance RISC-V Processor
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       SiFive P550 Core: High-Performance RISC-V Processor
        
       Author : andrewnc
       Score  : 145 points
       Date   : 2021-06-22 14:36 UTC (8 hours ago)
        
 (HTM) web link (www.sifive.com)
 (TXT) w3m dump (www.sifive.com)
        
       | zozbot234 wrote:
       | The press release mentions that this is a triple-issue OOO
       | design. Probably based on BOOM v3/SonicBOOM architecture[0],
       | given what we know of previous SiFive designs.
       | 
       | [0] https://github.com/riscv-boom/riscv-boom
        
         | FullyFunctional wrote:
         | From the press release:
         | 
         | "Evolved from the previously announced SiFive U84
         | microarchitecture,"
         | 
         | The U84 was a from scratch, in-house design.
        
       | ch_123 wrote:
       | I hope they release an update of the "Unmatched" motherboard with
       | one of these chips. I'm reluctant to spend ~$700 on a platform
       | which uses in-order cores which are presumably designed for low-
       | power devices.
       | 
       | (Yes, I appreciate I may not be the intended audience for that
       | board, but I would still like to build a RISC-V based desktop one
       | of these years)
        
         | JensensStapler wrote:
         | The P550 core in the title is actually a 3 way issue OOO core
         | with near A76 performance, but fair point on the dev boards.
         | Hopefully Intel's dev board or some alternative will provide a
         | lower cost option.
        
       | marcodiego wrote:
       | > said Amber Huffman, Intel Fellow and CTO of IP engineering
       | group at Intel.
       | 
       | Hope intel doesn't infect it with IME.
        
       | 1MachineElf wrote:
       | Hopefully the recent acquisition rumors don't spell the end of
       | this healthy competition between x86 and RISC-V.
       | 
       | I wonder what we'll see as a result of this partnership with
       | Intel:
       | 
       |  _SiFive also confirmed that the IFC RISC-V application
       | development platform will use the Performance P550 core on Intel
       | 's 7nm Horse Creek platform._
       | 
       | Link:
       | https://www.phoronix.com/scan.php?page=news_item&px=SiFive-P...
        
         | grlass wrote:
         | SiFive are definitely amongst the most interesting players in
         | RISC-V right now.
         | 
         | Though there other organisations doing things, e.g. the PULP
         | Platform: https://news.ycombinator.com/item?id=23768080
         | 
         | I hope that the acquisition doesn't go through, more
         | competition would be great, and perhaps within a decade a wider
         | commercial RISC-V ecosystem could emerge.
        
         | Koshkin wrote:
         | There is no "healthy competition between x86 and RISC-V".
        
           | nine_k wrote:
           | Only between RISC-V and ARM?
        
             | dragontamer wrote:
             | ARM is a collection of many different cores. So yes, RISC-V
             | probably competes well vs ARM-M, but I wouldn't say that
             | RISC-V competes against ARM-A (which is starting to become
             | big enough to compete against x86).
             | 
             | Just because ARM-M and ARM-A shares an instruction set
             | doesn't mean that those chips are anything alike. Heck,
             | ARM-M0+ is a completely different chip than ARM-M4.
             | 
             | ARM-R is roughly the target of RISC-V. (Realtime cores).
        
               | monocasa wrote:
               | The core in this article wouldn't be a very good ARM-R
               | core being OoO. It's about the same niche as an A72
               | AFAICT. So RISCV is already nipping at the heels of the
               | ARM application core space.
        
               | dragontamer wrote:
               | ARM Cortex R8 is out of order.
               | 
               | https://www.arm.com/products/silicon-ip-
               | cpu/cortex-r/cortex-...
        
               | monocasa wrote:
               | And AFAIK they didn't really get any takers there either
               | because it didn't really make sense. I think ARM was
               | hoping for a market of large legacy codebases (think cell
               | modems) where the heavy hard realtime work had been
               | migrated to fixed function IP blocks, DSPs, etc. years
               | ago, but the vendor didn't want to spend the time
               | migrating their RTOS to ARM-A from ARM-R for the
               | intermittent, non realtime, but still compute intensive
               | work. You can sort of see how they didn't get any uptake
               | with how the marketing changed pretty heavily with the
               | R82 towards storage vendors instead of 5G. And RISCV
               | doesn't have even the hope of that network effect to bank
               | on.
               | 
               | I'd also expect features like per core TCM if this core
               | was targeting ARM-R niches to at least break away from
               | the non determinism of the memory hierarchy (particularly
               | a multi core memory hierarchy!), but I don't see that
               | here.
        
               | nickik wrote:
               | There are multiple vendors now selling RISC-V products
               | that compete with ARM-A as well.
               | 
               | Its not as far alone as the lower end but it defiantly
               | happening as well.
        
           | creddit wrote:
           | Yeah, I really can't imagine how one would class it as
           | healthy let alone even a serious competition. x86 and ARM,
           | however, are starting to have a real battle with ARM owning
           | mobile, making headwinds into laptops and desktops at Apple
           | and multiple vendors producing meaningful server chips.
        
             | JensensStapler wrote:
             | Merchant ARM server is mostly dead unfortunately.
             | Hyperscalers like AWS are making their own SoCs in house
             | however. Amazona acquired Annapurna labs for that purpose.
             | 
             | Personally I see there being more market overlap between
             | ARM and the P550 core however. Samsung, Qualcomm, Renesas
             | are all planning to bring RISC-V cores to market. With
             | performance between A75 and A76, I could see the P550 being
             | a pretty major disruptor. We already know some RISC-V chips
             | are gaining traction in embedded, IoT, RF, micro-
             | controllers, etc. Automotive looks like the next big market
             | for RISC-V to me.
        
             | deelowe wrote:
             | ARM is making headwinds into server as well now.
        
               | monocasa wrote:
               | It's hard to tell apples->apples when you can't buy the
               | leading edge ARM servers outright AFAIK. There's a good
               | argument that it's in the hyperscalers' best interest to
               | discount ARM usage to even below their breakeven to put
               | negotiating pressure on their x86 core suppliers as long
               | as they balance the costs well enough.
        
           | trevortheblack wrote:
           | There was no "healthy competition between msn and google".
           | There was no "healthy competition between Blockbuster and
           | Netflix". There was no "healthy competition between Barnes &
           | Noble and Amazon".
           | 
           | Lack of competition today does not belie there never being
           | competition. I would argue that anti-trust should be taken
           | against killing/buying your competition when it's still in
           | the womb, see Instagram-v-Facebook, WhatsApp-v-Facebook,
           | InstagramStories-v-snapchat
        
       | zsmi wrote:
       | It's for sure an interesting result but honestly, perf/freq is
       | yesterday's spec. What matters in 2021 is perf/W and perf/$ and
       | there is no information on either of those metrics.
        
         | LargoLasskhyfv wrote:
         | What about perf/degree of safety?
        
         | plantsbeans wrote:
         | They mention "performance/area" as being dramatically better
         | than Cortex-A75. I'm not familiar with whether area is expected
         | to relate to power usage.
        
           | zsmi wrote:
           | perf/area comes with a huge number of caveats and it
           | basically doesn't mean anything as given.
           | 
           | For example, the exact same verilog, on the same process node
           | at the same foundry, can synthesize to very different areas
           | depending on the standard library used. They come in a lot of
           | varieties with a lot of different trade offs.
           | 
           | For even more detail, the SkyWater130 node, which has been
           | popular on HN lately and is public so we can actually post
           | links to it, has 6 different mappings that are possible.
           | Note, some are called high speed, or high density, etc. You
           | get the idea.
           | 
           | https://skywater-
           | pdk.readthedocs.io/en/latest/contents/libra...
        
           | wmf wrote:
           | SiFive likes to include just enough resources to do well on
           | their benchmark du jour (was dhrystone, now SPECint) and
           | leave out the rest. So they end up comparing an Arm core with
           | NEON against their RISC-V cores with no SIMD/vector support
           | for example.
        
             | seg_lol wrote:
             | Which is fine because what would normally be handled by the
             | SIMD will be custom silicon for most customers and have a
             | 4-100x speedup over what SIMD could provide.
        
             | zozbot234 wrote:
             | Previous cores had no vector support because the V
             | extension that provides for it was nowhere close to being
             | standardized. In fact it's yet to be ratified at present,
             | so one may want to wait for that before choosing a
             | V-capable core for real, actual use.
        
             | chriscappuccio wrote:
             | "The SiFive Performance P270 is an 8-stage, dual-issue,
             | highly efficient in-order pipeline compatible with the
             | RISC-V RV64GCV ISA. With full support for the RISC-V Vector
             | Extension v 1.0RC, and combined with SiFive Recode, which
             | translates existing SIMD software from popular legacy
             | architectures to RISC-V Vector assembly code, the SiFive
             | Performance P270 is an ideal replacement for dated SIMD
             | architectures."
        
           | meepmorp wrote:
           | I'm not even why we're supposed to care about a newly
           | launched core beating one that was released in 2017. If
           | that's the bar they've set, I'm not exactly wowed.
        
             | NortySpock wrote:
             | Gotta start somewhere
        
             | nickik wrote:
             | Because the ARM core still has a large market and not every
             | application need the maximum performance so having
             | competition in that market is not good.
             | 
             | And you are not 'supposed to' care. You can care if you
             | want, and ignore it if you want. So I don't really get your
             | attitude here.
        
           | ksec wrote:
           | >They mention "performance/area" as being dramatically better
           | than Cortex-A75.
           | 
           | The P550 pref / area based on Intel 7nm equivalent to TSMC
           | 4nm / 3nm that is better than the ARM Cortex A75 released in
           | 2017 on TSMC 10nm.
           | 
           | Number using Intel CPU's 7nm, normally Custom Foundry of IFS
           | tends to offer lower density but higher flexibility. So this
           | is more like a best case scenario.
           | 
           | I am also suspicious of the Intel 7nm number. There are some
           | possibility this is actually an Intel 10nm renamed to 7nm for
           | custom foundry partners. ( Intel 10nm being equivalent to
           | TSMC 7nm )
        
             | JensensStapler wrote:
             | No, the area numbers quoted are for TSMC N7. You can look
             | up comparable A75 die area numbers for N7 as well. A Cortex
             | A76 on TSMC N7 takes up 1.27mm with L2 included. A P550
             | takes up 0.38mm.
        
       | truncate wrote:
       | How does RISC-V places itself in market? What would be the
       | advantage of going RISC over let say ARM (or x86)?
        
         | forgotpwd16 wrote:
         | RISC-V is license and royalty-free. This provides more freedom
         | to manufacturers to experiment and optimize for specific
         | workloads something helped by RISC-V's modular design. Also its
         | simpler design makes it attractive to hobbyists as well.
        
           | CameronNemo wrote:
           | But in this case (SiFive) the core IP is proprietary.
           | 
           | So what makes this better than an ARM A78 or X1?
        
         | MangoCoffee wrote:
         | as backup incase Nvidia manage to buy ARM and squeeze all the
         | fabless companies
        
           | CameronNemo wrote:
           | And what if Intel buys SiFive and we are back to stunted
           | RISC-V cores?
        
       | nickik wrote:
       | Go work with System76 and get me a RISC-V RV64GCV Laptop. That
       | would be awesome.
        
         | xvilka wrote:
         | And a tablet computer.
        
           | kingsuper20 wrote:
           | and a little desktop box. Gotta be quicker than a Raspberry
           | PI 4 though.
        
           | rwmj wrote:
           | AllWinner will likely deliver one of those in the near
           | future.
        
             | eric__cartman wrote:
             | If they do I hope those chips get better mainline Linux
             | kernel support than the ARM based ones. The work the
             | Armbian devs are doing is amazing, but they are still
             | missing drivers from the manufacturer. Mainly for proper
             | graphics and video encoding/decoding. The only operating
             | system where this works well is in Android with an archaic
             | kernel.
        
               | FullyFunctional wrote:
               | The _CPU_ support is already pretty good and for example
               | Huawei is pushing important Linux kernel patches.
               | 
               | What you are talking about is drivers for peripherals,
               | which is are SoC-level issues, and really up to the
               | partners (like Allwinner, SiPeed, etc). So far
               | documentation is the most critical part and it's a very
               | mixed bag. I think this will be much like the Arm
               | experience, albeit everyone is at least using device
               | trees these days.
        
             | FullyFunctional wrote:
             | I have a C906 and while it's fun, it's very very slow by
             | 2021 standards: single core, scalar in-order @ 1.0 GHz with
             | no L2$.
             | 
             | The upcoming BeagleV is a lot faster (I have the beta):
             | quad core, dual issue in-order @1.5 GHz (TBD) with 2 MiB
             | L2.
             | 
             | I'm expecting (guessing) that the triple-issue OoO P550
             | would be 5-10X faster at iso-frequency, but if history
             | repeats it'll be four+ years before we see it in silicon
             | for sale.
        
         | marcodiego wrote:
         | Anything RYF certified. Nevermind the manufacturer.
        
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