[HN Gopher] NEORV32: A customizable RISC-V SoC
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       NEORV32: A customizable RISC-V SoC
        
       Author : _quarks_
       Score  : 49 points
       Date   : 2021-06-23 17:21 UTC (5 hours ago)
        
 (HTM) web link (blog.adafruit.com)
 (TXT) w3m dump (blog.adafruit.com)
        
       | ffhhj wrote:
       | Where or when can we get these chips/boards?
        
         | Narishma wrote:
         | The github readme lists at least 3 FPGA boards you can use.
        
       | kken wrote:
       | Why not link to the GitHub?`
       | 
       | https://github.com/stnolting/neorv32
       | 
       | Also the Documentation
       | 
       | https://stnolting.github.io/neorv32/
       | 
       | This is absolutely one of the best documented free hardware
       | projects that I have ever seen. Most company documentation is
       | worse by far.
        
         | api wrote:
         | It's not hard to do better than typical hardware vendor
         | documentation.
        
         | UncleOxidant wrote:
         | Wow, that _is_ good documentation. And it 's VHDL too (which I
         | prefer to Verilog).
        
           | wyager wrote:
           | IMO, VHDL and Verilog are both outstandingly terrible. There
           | are tons of good options that compile from another language
           | _to_ VHDL /Verilog, such as Clash, Chisel, and nmigen. I
           | cannot recommend strongly enough to use any of those over
           | VHDL or Verilog.
           | 
           | My personal favorite is Clash - it's unusual in that it
           | actually compiles the host language (a subset of Haskell)
           | into VHDL/Verilog, rather than simply providing a library
           | which you can use to create circuit objects. This means you
           | can compile your hardware and run it like a normal program,
           | or include it as a library, or whatever. Very nice for
           | testing. You can also use arbitrary libraries as long as you
           | don't use anything that falls outside the compilable subset.
        
             | UncleOxidant wrote:
             | I'm kind of torn on the alternative HDLs. The HDL code they
             | generate is often not very readable. When you're simulating
             | you're effectively debugging that generated code. Generate
             | statements in VHDL/System Verilog can often cover some of
             | the use cases. Mostly I find them useful for testbench
             | generation - that seems to be where things like Cocotb
             | really shine.
        
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       (page generated 2021-06-23 23:01 UTC)