[HN Gopher] Silicon die teardown: a look inside an early 555 tim...
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Silicon die teardown: a look inside an early 555 timer chip
Author : picture
Score : 82 points
Date : 2022-01-24 17:13 UTC (5 hours ago)
(HTM) web link (www.righto.com)
(TXT) w3m dump (www.righto.com)
| 0xTJ wrote:
| Working with modern technologies, it's incredible to me that the
| transistors are on the same order of scale as the bond-out pads.
| puzzlingcaptcha wrote:
| "But for a variety of reasons, PNP transistors have an entirely
| different construction." - Can you expand on what some of those
| reasons are? And why is the emitter in a PNP circular?
| kens wrote:
| Theoretically you could make a PNP transistor by reversing the
| doping of an NPN transistor. The main problem is that boron
| diffuses rapidly, making it hard to fabricate a buried P-layer.
| Boron also has less solubility than phosphorus, making it hard
| to dope the emitter. Also, holes have only 1/3 the mobility of
| electrons, so PNP and NPN aren't symmetrical. To deal with
| these issues, PNP transistors are usually built with lateral
| construction (i.e. horizontally). The ring structure ensures
| that almost all of the carriers injected by the emitter are
| intercepted by the collector.
|
| (This is based on The Art of Analog Layout, p280. I don't know
| all this doping stuff myself.)
| puzzlingcaptcha wrote:
| Thanks! I also have to say that you have a very accessible
| writing style for what is a rather convoluted topic and that
| the interactive schematic tool is a great aid.
| morei wrote:
| What's the difference between N and N+ ? As far as I can tell, N+
| just means a higher doping concentration? But it seems very fuzzy
| as to what 'higher' means?
| kens wrote:
| Yes, N+ and P+ are just heavily doped regions.
| commandlinefan wrote:
| Wow, I always assumed that the actual "live" part of the chips
| were most of the packaging - the second picture makes it look
| like the chip is 99% epoxy packaging and 1% silicon. Is that
| right? Is that typical? Is the packaging that big to separate the
| pins from each other or just to make it something humans can
| handle/keep track of?
| jacquesm wrote:
| The connections can take up the bulk of the package.
| andyjohnson0 wrote:
| > Is the packaging that big to separate the pins from each
| other
|
| Yes. DIP packages have standard pin spacings.
|
| https://en.wikipedia.org/wiki/Dual_in-line_package
| spear wrote:
| Sometimes, the silicon die itself may be "pad-limited", ie. the
| minimum size is determined by the number of I/O pads on the
| die, which have their own spacing requirements.
| jaywalk wrote:
| This holds true even on current CPUs, although they're
| obviously not packaged in the same way.
| kens wrote:
| Back then, printed circuit board technology wasn't as advanced
| so chips usually had 0.1" spacing so there was room for the PCB
| traces. The chip's package was much larger than the silicon.
| Nowadays, in something like a phone, you want the packages to
| be as small as possible. You can now get a 555 timer in a
| package that is 1.4mm on a side, which is not a lot bigger than
| the silicon die, but still limited by the spacing of the solder
| balls.
| mwattsun wrote:
| Giant 555 Timer using discrete components
|
| https://hackaday.io/project/182863-giant-555-timer
| ohazi wrote:
| Similarly, a giant 555 Timer using vacuum tubes!
|
| https://www.youtube.com/watch?v=bjAlzA4Cyys
| Dinux wrote:
| I was thinking exactly this when reading the article. thanks
| kens wrote:
| Author here for all your chip questions...
| mikebco wrote:
| What kind of chip layout/validation tools and methods would
| have been used for this chip? The layout does not appear to be
| as dense or uniform as other chip images that I've seen. Is the
| large spacing between elements more indicative of a prototype
| that would have been refined later in production?
| kens wrote:
| The chip was designed in 1971, so layout would have been
| drawing it on a large piece of paper and then cutting the
| masks out of sheets of plastic (Rubylith).
|
| The layout looks typical for that era. Keep in mind that this
| is an analog chip, so resistors take up a lot of space. Also,
| with just 24 transistors, you don't need to squeeze every bit
| out of the layout. I've looked at other versions of the 555
| timer and the layout isn't much better. Even the CMOS 555 has
| a lot of wasted space.
| winstongator wrote:
| Thanks for posting. Love your stuff!
| showerst wrote:
| Any particular favorite book or course recommendations for
| learning about vintage (or current) IC design? I'm not looking
| to go into the field, just programmer who thinks being able to
| puzzle out things like die shots is really cool.
| kens wrote:
| I stick to ICs from the 1970s and 1980s; after that, things
| get too hard to understand. Books from that era provide a
| reasonable description.
|
| For digital circuits, Mead and Conway's Introduction to VLSI
| Systems is a good source of information. It's available
| online: https://ai.eecs.umich.edu/people/conway/VLSI/VLSIText
| /VLSITe... (the link seems to be down right now, though.)
|
| For analog circuits, the book "The Art of Analog Layout" is
| good if you can find a cheap used copy. The designer of the
| 555 timer wrote an interesting book "Designing Analog Chips"
| which I found very interesting. It is available online:
| http://www.designinganalogchips.com/
|
| There's also an online tutorial on IC reverse engineering:
| http://siliconzoo.org/tutorial.html
| showerst wrote:
| Thanks so much!
| tadbit wrote:
| Do you have a layman's explanation for what the 555 timer is
| used for and how it works?
| colejohnson66 wrote:
| It's such a simple IC that it's hard to see what it can do.
| But if you stick some resistors and capacitors around it in
| just the right ways, it can do so much. Google "555 examples"
| for _thousands_ of example schematics. Wikipedia has a few
| examples: https://en.wikipedia.org/wiki/555_timer_IC#Modes
| [deleted]
| kens wrote:
| The basic idea of the 555 timer is to generate a pulse of a
| fixed timing, from microseconds to hours. But it is a very
| flexible chip so it has hundreds of applications, operating
| as anything from a timer or latch to a voltage-controlled
| oscillator or modulator. As a result, the chip was very
| widely used.
|
| How it works is that when you charge a capacitor through a
| resistor, the capacitor will charge relatively slowly. The
| rate depends on the value of the components. What the 555
| chip does is monitors the voltage level on the capacitor.
| When it reaches an upper level, the chip discharges the
| capacitor. When the voltage reaches a lower level, the chip
| starts charging the capacitor. Thus you get oscillations with
| the desired timing.
|
| Think of it kind of like filling your sink with water. When
| the sink gets 2/3 full, you pull the plug from the drain.
| When the water level drops to 1/3, you put the plug back in
| the drain. This will give you periodic oscillations. The
| timing depends on the size of the sink (capacitor) and how
| much you open the tap (resistor).
| tadbit wrote:
| This is a fantastic explanation. Thank you!
| yesimahuman wrote:
| Remarkable how such a simple chip can be so complicated. And to
| think how complex modern CPUs/etc. are in comparison!
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