[HN Gopher] How close is RISC-V to RISC-I? (2017) ___________________________________________________________________ How close is RISC-V to RISC-I? (2017) Author : cpeterso Score : 37 points Date : 2022-11-04 20:33 UTC (1 days ago) (HTM) web link (web.archive.org) (TXT) w3m dump (web.archive.org) | kragen wrote: | Much closer than I would have expected. But what's this about | RISC-V not having a jump with a register and offset address? | Doesn't JALR have a 12-bit offset that's added to the base | register rs1? How is that different from RISC-I's JMP COND, | S2(Rx)? Does COND mean the jump is conditional, like JMPR EQ? | | Interestingly since this article most of the "In RISC-V, but not | RISC-I" instructions have been moved to extensions: Zicsr for the | CSR instructions and Zifencei for the FENCE.I instruction (which | turns out not to be useful for user processes running on a | multicore processor with a multitasking OS like FreeBSD or | Linux). That leaves only AUIPC, SBREAK (now called EBREAK), and | FENCE. So it's even closer now than it was in 02017. | Y_Y wrote: | Had anyone tried to find (or derive) an ideal set of instructions | for a processor architecture, with any assumptions about | arithmetic etc? For example you can try to minimise the number of | instructions it takes to encode some set of nontrivial program. | (Of course how this would translate to silicon is another | question.) ___________________________________________________________________ (page generated 2022-11-05 23:00 UTC)