[HN Gopher] Bulldozer, AMD's Crash Modernization: Caching and Co... ___________________________________________________________________ Bulldozer, AMD's Crash Modernization: Caching and Conclusion Author : gautamcgoel Score : 7 points Date : 2023-01-24 22:00 UTC (1 hours ago) (HTM) web link (chipsandcheese.com) (TXT) w3m dump (chipsandcheese.com) | johnklos wrote: | This clarifies a bit the dispute about AMD's settlement about the | core count lawsuit. The one FPU per cluster of two cores is what | I've always thought decided the case, and observations like these | continue to point out that the two individual integer cores | didn't share enough to impede either's resources: | | > When running two threads in the module, Bulldozer can provide | twice as much > L2 bandwidth. That suggests the L2 has separate | paths to each thread's > load/store unit, and lines up with AMD's | publications. | | I never knew that the 32 nm process had so many issues. They | certainly were never as bad as the 90 nm issues, but perhaps | after all the noise about 90 nm, problems with 32 nm just weren't | worth writing about in the news. | | I wonder if my specific needs just matched the Bulldozer CPU | particularly well, because I didn't see any significant | advantages in Sandy Bridge over Bulldozer. Then again, I was | running four concurrent but separate threads of -J 2 compiles | simultaneously, which may've been a particularly good use case | for Bulldozer. | | I think I'll try out some new benchmarks using a modern OS and | toolchain on both Sandy Bridge and Bulldozer to see how things | have changed since 2011 / 2012. | chaimanmeow wrote: | good link and read but dup | | https://news.ycombinator.com/item?id=34482667 | | My 2 cents, | | I'd like to see Zen 2 merged with some CMT ingenuity for their | low power high efficiency branch of cores. Introduce some | clustering on one of these Zen 2 CCXs, and arrange this cluster | with SMT4 on the FPU side while keeping SMT2 on the integer side. | This would be an analogue to the Piledriver family's SMT1/SMT2 | int/fpu scheme. | gautamcgoel wrote: | It's not a dup, that's Part I of the article, this is Part II. | chaimanmeow wrote: | oh thanks and sorry! more to catch up on reading then!! sorry | for my oops. | pvg wrote: | follow-ons (usually) count as dupes so it would be an HN | dupe if it had significant discussion but it doesn't so | it's not. | [deleted] ___________________________________________________________________ (page generated 2023-01-24 23:00 UTC)