68060 Cycles

Last Updated: 01 October 1998
68060 Instruction Times
Typed and HTML version by Scorpion/Silicon
Effective Address Calculation Times
Move Byte and Word Execution Times
Move Long Execution Times
Move16 Execution Times
Standard Instruction Execution Times
Immediate Instruction Execution Times
Single-Operand Instruction Execution Times
Clear (CLR) Execution Times
Shift/Rotate Execution Times
Bit Manipulation (Dynamic Bit Count) Execution Times
Bit Manipulation (Static Bit Count) Execution Times
Bit Field Execution Times
Branch Execution Times
JMP, JSR Execution Times
Return Instruction Times
LEA, PEA and MOVEM Instruction Execution Times
Multiprecision Instruction Execution Times
Status Register (SR) Instruction Execution Times
MOVES Execution Times>
Miscellaneous Instruction Execution Times
Floating-Point Instruction Execution Times
Exception Processing Times
Effective Address Calculation Times
Dn0(0/0)
An0(0/0)
(An)0(0/0)
(An)+0(0/0)
-(An)0(0/0)
(d16,An)0(0/0)
(d8,An,Xi*SF)0(0/0)
(bd,An,Xi*SF)1(0/0)
([bd,An,Xn],od)3(1/0)
([bd,An],Xn,od)3(1/0)
(xxx).W0(0/0)
(xxx).L0(0/0)
(d16,PC)0(0/0)
(d8,PC,Xi*SF)0(0/0)
(bd,PC,Xi*SF)1(0/0)
#data0(0/0)
([bd,PC,Xn],od)3(1/0)
([bd,PC],Xn,od)0(0/0)
Move Byte and Word Execution Times
SourceDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF)(xxx).WL
Dn1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
An1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
(An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(An)+1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
-(An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d16,An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d8,An,Xi*SF)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(bd,An,Xi*SF)2(1/0)2(1/0)3(1/1)3(1/1)3(1/1)4(1/1)3(1/1)4(1/1)3(1/1)
(xxx).W1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(xxx).L1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d16,PC)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d8,PC,Xi*SF)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(bd,PC,Xi*SF)2(1/0)2(1/0)3(1/1)3(1/1)3(1/1)4(1/1)3(1/1)4(1/1)3(1/1)
#data1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)2(0/1)2(0/1)3(0/1)2(0/1)
Move Long Execution Times
SourceDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF)(xxx).WL
Dn1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
An1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
(An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(An)+1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
-(An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d16,An)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d8,An,Xi*SF)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(bd,An,Xi*SF)2(1/0)2(1/0)3(1/1)3(1/1)3(1/1)4(1/1)3(1/1)4(1/1)3(1/1)
(xxx).W1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(xxx).L1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d16,PC)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(d8,PC,Xi*SF)1(1/0)1(1/0)2(1/1)2(1/1)2(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
(bd,PC,Xi*SF)2(1/0)2(1/0)3(1/1)3(1/1)3(1/1)4(1/1)3(1/1)4(1/1)3(1/1)
#data1(0/0)1(0/0)1(0/1)1(0/1)1(0/1)2(0/1)2(0/1)3(0/1)2(0/1)
MOVE16 Execution times
SourceDestination
(Ax)(Ax)+(xxx).L
(Ay)--18(1/1)
(Ay)+-18(1/1)18(1/1)
(xxx).L18(1/1)18(1/1)-
These execution times assume cache misses for both read
and write MOVE16 accesses. Execution times are 11(1/1) if
the read access hits in the operand data cache. Note, for
this instruction the operand read/write refers to a
line-sized transfer.
Standard Instruction Execution Time
InstructionSizeop <ea>,An (1)op <ea>,Dnop Dn,<M>
AddByte,Word1(1/0)1(1/0)1(1/1)
"Long1(1/0)1(1/0)1(1/1)
AndByte,Word-1(1/0)1(1/1)
"Long-1(1/0)1(1/1)
CmpByte,Word1(1/0)1(1/0)1(1/1)
"Long1(1/0)1(1/0)-
DivsWord-<=22(1/0) (2)-
"Long(3)-38(1/0)-
DivuWord-<=22(1/0) (2)-
"Long(3)-38(1/0)-
EorByte,Word-1(1/0)1(1/1)
"Long-1(1/0)1(1/1)
MulsWord-2(1/0)-
"Long(3)-2(1/0)-
MuluWord-2(1/0)-
"Long(3)-2(1/0)-
orByte,Word-1(1/0)1(1/1)
"Long-1(1/0)1(1/1)
SubByte,Word1(1/0)1(1/0)1(1/1)
"Long1(1/0)1(1/0)1(1/1)
(1) For entries in this column, add one cycle if the <ea>
is (Ay)+,-(Ay) and (Ay)=An
(2) Word divides have conditionnal exit points
(3) Add one cycle to the effective address calculation time for
all addressing modes except Rn,(An),(An)+,-(An),(d16,An) and (d16,PC)
Immediate Instruction Execution Times
InstructionSizeDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (1)(xxx).WL
AddiByte,Word1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
AddqByte,Word1(0/0)1(0/0)1(1/1)1(1/1)1(1/1)1(1/1)1(1/1)2(1/1)1(1/1)
"Long1(0/0)1(0/0)1(1/1)1(1/1)1(1/1)1(1/1)1(1/1)2(1/1)1(1/1)
AndiByte,Word1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
CmpiByte,Word1(0/0)-1(1/0)1(1/0)1(1/0)2(1/0)2(1/0)3(1/0)2(1/0)
"Long1(0/0)-1(1/0)1(1/0)1(1/0)2(1/0)2(1/0)3(1/0)2(1/0)
EoriByte,Word1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
MoveqLong1(0/0)--------
OriByte,Word1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
SubiByte,Word1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)-1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
SubqByte,Word1(0/0)1(0/0)1(1/1)1(1/1)1(1/1)1(1/1)1(1/1)2(1/1)1(1/1)
"Long1(0/0)1(0/0)1(1/1)1(1/1)1(1/1)1(1/1)1(1/1)2(1/1)1(1/1)
(1) Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Single Operand Instruction Execution Times
InstructionSizeRegisterMemory
CasByte,Word(1)-19(1/1)
"Long(1)-19(1/1)
NbcdByte1(0/0)1(1/1) (2)
NegByte,Word1(0/0)1(1/1) (2)
"Long1(0/0)1(1/1) (2)
NegxByte,Word1(0/0)1(1/1) (2)
"Long1(0/0)1(1/1) (2)
NotByte,Word1(0/0)1(1/1) (2)
"Long1(0/0)1(1/1) (2)
SccByte->False1(0/0)1(1/1) (2)
"Byte->True1(0/0)1(1/1) (2)
TasByte1(0/0)17(1/1) (2)
TstByte,Word1(0/0)1(1/0) (2)
"Long1(0/0)1(1/0) (2)
(1) Add (1+ Effective address calculation time) cycle for all
addressing modes except Rn,(An),(An)+,-(An) and (d16,An).
(2) Add the effective address calculation time to these
instructions.
Clear (CLR) Execution Times
SizeDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (1)(xxx).WL
Byte,Word1(0/0)-1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
Long1(0/0)-1(0/1)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)1(0/1)
(1) Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Shift/Rotate Execution Times
InstructionSizeRegisterMemory (1)
Asl,AsrByte,Word1(0/0)1(1/1)
"Long1(0/0)-
Lsl,LsrByte,Word1(0/0)1(1/1)
"Long1(0/0)-
Rol,RorByte,Word1(0/0)1(1/1)
"Long1(0/0)-
Roxl,RoxrByte,Word1(0/0)1(1/1)
"Long1(0/0)-
(1) For entries in this column, add the effective address
calculation time. These operations are word-size only.
Bit manipulation (Dynamic Bit Count) Execution Times
InstructionSizeRegisterMemory (1)
BchgByte-1(1/1)
"Long1(0/0)-
BclrByte-1(1/1)
"Long1(0/0)-
BsetByte-1(1/1)
"Long1(0/0)-
BtstByte-1(1/1)
"Long1(0/0)-
(1) For entries in this column, add the effective
address calculation time.
Bit manipulation (Static Bit Count) Execution times
InstructionSizeDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (1)(xxx).WL
BchgByte--1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)--------
BclrByte--1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)--------
BsetByte--1(1/1)1(1/1)1(1/1)2(1/1)2(1/1)3(1/1)2(1/1)
"Long1(0/0)--------
BtstByte--1(1/0)1(1/0)1(1/0)2(1/0)2(1/0)3(1/0)2(1/0)
"Long1(0/0)--------
(1) Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Bit Field Execution Times (1)
InstructionDestination
DnAn(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (2)(xxx).WL
Bfchg (<5 bytes)8(0/0)-8(2/1)--8(2/1)9(2/1)10(2/1)9(2/1)
Bfchg (=5 bytes)12(0/0)-12(4/2)--12(4/2)13(4/2)14(4/2)13(4/2)
Bfclr (<5 bytes)8(0/0)-8(2/1)--8(2/1)9(2/1)10(2/1)9(2/1)
Bfclr (=5 bytes)12(0/0)-12(4/2)--12(4/2)13(4/2)14(4/2)13(4/2)
Bfexts (<5 bytes)6(0/0)-6(1/0)--6(1/0)7(1/0)8(1/0)7(1/0)
Bfexts (=5 bytes)8(0/0)-8(2/0)--8(2/0)9(2/0)10(2/0)9(2/0)
Bfextu (<5 bytes)6(0/0)-6(1/0)--6(1/0)7(1/0)8(1/0)7(1/0)
Bfextu (=5 bytes)8(0/0)-8(2/0)--8(2/0)9(2/0)10(2/0)9(2/0)
Bfffo (<5 bytes)9(0/0)-9(1/0)--9(1/0)10(1/0)11(1/0)10(1/0)
Bfffo (=5 bytes)11(0/0)-11(2/0)--11(2/0)12(2/0)13(2/0)12(2/0)
Bfins (<5 bytes)6(0/0)-6(1/1)--6(1/1)7(1/1)8(1/1)7(1/1)
Bfins (=5 bytes)6(0/0)-6(2/2)--6(2/2)7(2/2)8(2/2)7(2/2)
Bfset (<5 bytes)8(0/0)-8(2/1)--8(2/1)9(2/1)10(2/1)9(2/1)
Bfset (=5 bytes)12(0/0)-12(4/2)--12(4/2)13(4/2)14(4/2)13(4/2)
Bftst (<5 bytes)6(0/0)-6(1/0)--6(1/0)7(1/0)8(1/0)7(1/0)
Bftst (=5 bytes)8(0/0)-8(2/0)--8(2/0)9(2/0)10(2/0)9(2/0)
(1) The type of offset and width (static,dynamic) does not
affect the execution time.
(2) Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Branch Execution Times
InstructionNot
Predicted,
Forward,
Taken		Not
Predicted,
Forward,
Not Taken		Not
Predicted,
Backward,
Taken		Not
Predicted,
Backward,
Not Taken		Predicted
Correctly as
Taken		Predicted
Correctly as
Not Taken		Predicted
Incorrectly
Bcc7(0/0)1(0/0)3(0/0)7(0/0)0(0/0)1(0/0)7(0/0)
Bra3(0/0)-3(0/0)-0(0/0)--
Bsr3(0/1)-3(0/1)-1(0/1)--
Dbcc3(0/0)8(0/0)3(0/0)8(0/0)2(0/0)2(0/0)8(0/0)
Dbra3(0/0)7(0/0)3(0/0)7(0/0)1(0/0)1(0/0)7(0/0)
Fbcc8(0/0)2(0/0)8(0/0)2(0/0)2(0/0)2(0/0)8(0/0)
JMP,JSR Execution times (1)
InstructionNot
Predicted,
Forward,
Taken		Not
Predicted,
Forward,
Not Taken		Not
Predicted,
Backward,
Taken		Not
Predicted,
Backward,
Not Taken		Predicted
Correctly as
Taken		Predicted
Correctly as
Not Taken		Predicted
Incorrectly
Jmp (d16,PC)3(0/0)-3(0/0)-0(0/0)--
Jmp xxx.WL3(0/0)-3(0/0)-0(0/0)--
Remaining Jmp5(0/0)-5(0/0)-5(0/0)--
Jsr (d16,PC)3(0/1)-3(0/1)-1(0/1)--
Jsr xxx.WL3(0/1)-3(0/1)-1(0/1)--
Remaining Jsr5(0/1)-5(0/1)-5(0/1)--
(1) Add the effective address calculation time for each entry
Return Instruction Execution Times
InstructionExecution Time
Rtd7(1/0)
Rte17(3/0)
Rtr8(2/0)
Rts7(1/0)
LEA, PEA and MOVEM Instruction Times
Instruction(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (1)(xxx).WL(d16,PC)(d8,PC,Xi*SF)(bd,PC,Xi*SF) (1)
Lea1(0/0)--1(0/0)1(0/0)2(0/0)1(0/0)1(0/0)1(0/0)2(0/0)
Pea1(0/1)--2(0/1)2(0/1)3(0/1)1(0/1)1(0/1)2(0/1)2(0/1)
Movem Mem->Regn(n/0)n(n/0)-n(n/0)1+n(n/0)2+n(n/0)1+n(n/0)n(n/0)1+n(n/0)2+n(n/0)
Movem Reg->Memn(0/n)-n(0/n)n(0/n)1+n(0/n)2+n(0/n)1+n(0/n)---
(1) Add 2(1/0) cyles to the (bd,{An,PC},Xi*SF) time for a memory
indirect address
"n" is the number of registers being moved.
Multiprecision Instruction Times
InstructionSizeop Dy,Dxop <ea>y,<ea>x (1)
AddxByte,Word1(0/0)2(2/1)
"Long1(0/0)2(2/1)
CmpmByte,Word-2(2/0)
"Long-2(2/0)
SubxByte,Word1(0/0)2(2/1)
"Long1(0/0)2(2/1)
AbcdByte1(0/0)2(2/1)
SbcdByte1(0/0)2(2/1)
(1) Where <ea>x is (Ay)+,(Ax)+ for Cmpm and -(Ay),-(Ax)
for all other instructions.
Status Register (SR) Instruction Execution Times
InstructionExecution Time
Andi to Sr12(0/0)
Eori to Sr12(0/0)
Move from Sr1(0/0) (1)
Move to Sr12(1/0) (1)
Ori to Sr5(0/0)
(1)For these instructions, add the effective address calculation times
MOVES Execution Times
MOVES FunctionDestination
Size(An)(An)+-(An)(d16,An)(d8,An,Xi*SF)(bd,An,Xi*SF) (1)(xxx).WL
Source<SFC>->RnByte,Word1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)
"Long1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)
Rn->Dest<DFC>Byte,Word1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)3(0/1)2(0/1)
"Long1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)3(0/1)2(0/1)
(1) Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Miscellaneous Instruction Execution Times
InstructionSizeRegisterMemoryReg->DestSource->Reg
Andi to CCRByte1(0/0)---
ChkWord2(0/0)2(1/0) (1)--
"Long2(0/0)2(1/0) (1)--
Cinva--<=17(0/0)--
Cinvl--<=18(0/0)--
Cinvp--<=274(0/0)--
Cpusha--<=5394(0/512) (2)--
Cpushl--<=26(0/1) (2)--
Cpushp--<=2838(0/256) (2)--
Eori to CCRByte1(0/0)---
ExgLong1(0/0)---
ExtWord1(0/0)---
"Long1(0/0)---
ExtbLong1(0/0)---
LinkWord2(0/1)---
"Long2(0/1)---
LpstopWord15(0/1)---
Move from CCRWord1(0/0)1(0/1) (1)--
Move to CCRWord1(0/0)1(1/0) (1)--
Move from USPLong1(0/0)---
Move to USPLong2(0/0)---
Movec (SFC,DFC,USP,VBR,PCR)Long--12(0/0)11(0/0)
Movec (CACR,TC,TTR,BUSCR,URP,SRP)Long--15(0/0)14(0/0)
Nop-9(0/0)---
Ori to CCRByte1(0/0)---
Pack-2(0/0)2(1/1)--
Plpa (ATC hit)-15(0/0)---
Plpa (ATC miss)-28(0/0)---
Pflush-18(0/0)---
Pflushn-18(0/0)---
Pflushan-33(0/0)---
Pflusha-33(0/0)---
Reset-520(0/0)---
StopWord8(0/0)---
SwapWord1(0/0)---
Trapf-1(0/0)---
Trapcc-1(0/0)---
Trapv-1(0/0)---
Unlk-1(1/0)---
Unpk-2(0/0)2(1/1)--
(1) for these entries, add the effective address calculation time
(2) For the CPUSH instruction, the operand write figure refers to
line-sized transfers.
Floating-Point Instruction Execution Times
InstructionEffective Address
FPnDn(An)(An)+-(An)(d16,An)
(d16,PC)		(d8,An,Xi*SF)
(d8,PC,Xi*SF)		(bd,An,Xi*SF)
(bd,PC,Xi*SF)		(xxx).WL#<imm>
FAbs1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FDAbs1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FSAbs1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FAdd3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FDAdd3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FSAdd3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FCmp1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FDiv37(0/0)39(0/0)37(1/0)37(1/0)37(1/0)37(1/0)38(1/0)39(1/0)38(1/0)38(0/0)
FDDiv37(0/0)39(0/0)37(1/0)37(1/0)37(1/0)37(1/0)38(1/0)39(1/0)38(1/0)38(0/0)
FSDiv37(0/0)39(0/0)37(1/0)37(1/0)37(1/0)37(1/0)38(1/0)39(1/0)38(1/0)38(0/0)
FMove ,FPx1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)1(0/0)
FDMove ,FPx1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)1(0/0)
FSMove ,FPx1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)1(0/0)
FMove FPy,-3(0/0)1(0/1)1(0/1)1(0/1)1(0/1)2(0/1)3(0/1)2(0/1)-
FMove ,FPCR-8(0/0)6(1/0)6(1/0)6(1/0)6(1/0)7(1/0)8(1/0)7(1/0)7(0/0)
FMove FPCR,-4(0/0)2(0/1)2(0/1)2(0/1)2(0/1)3(0/1)4(0/1)3(0/1)-
FInt3(0/0)4(0/0)3(1/0)3(1/0)3(1/0)3(1/0)3(1/0)5(1/0)3(1/0)3(0/0)
FIntrz3(0/0)4(0/0)3(1/0)3(1/0)3(1/0)3(1/0)3(1/0)5(1/0)3(1/0)3(0/0)
FSGLDiv37(0/0)39(0/0)37(1/0)37(1/0)37(1/0)37(1/0)38(1/0)39(1/0)38(1/0)38(0/0)
FSGLMul3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FMovem ,FPx *--1+3n(3n/0)1+3n(3n/0)-1+3n(3n/0)2+3n(3n/0)3+3n(3n/0)2+3n(3n/0)-
FMovem FPy, *--1+3n(0/3n)-1+3n(0/3n)1+3n(0/3n)2+3n(0/3n)3+3n(0/3n)2+3n(0/3n)-
FMul3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FDMul3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FSMul3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FNeg1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FDNeg1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FSNeg1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FSub3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FDSub3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FSSub3(0/0)5(0/0)3(1/0)3(1/0)3(1/0)3(1/0)4(1/0)5(1/0)4(1/0)4(0/0)
FTst1(0/0)3(0/0)1(1/0)1(1/0)1(1/0)1(1/0)2(1/0)3(1/0)2(1/0)2(0/0)
FSqrt68(0/0)70(0/0)68(1/0)68(1/0)68(1/0)68(1/0)69(1/0)70(1/0)69(1/0)69(1/0)
FDSqrt68(0/0)70(0/0)68(1/0)68(1/0)68(1/0)68(1/0)69(1/0)70(1/0)69(1/0)69(1/0)
FSSqrt68(0/0)70(0/0)68(1/0)68(1/0)68(1/0)68(1/0)69(1/0)70(1/0)69(1/0)69(1/0)
FSave--3(0/3)-------
FRestore--6(3/0)-------
FMovem ,FPxR--7(n/0)-------
FMovem FPxR,--5(0/n)-------
"n" is the number of registers being moved.
For ALL FPU operations, if the external operand format is byte,word
or long add three cycles to the execution time.
* For ALL FPU operations except FMOVEM, if the external operand
format is extended precision, add two cycles to the excution time.
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for
a memory indirect address.
Add 1(0/0) cycle if the <ea> specifies
a double precision immediate operand.
Exception Processing Times
ExceptionExecution Time
Cpu Reset45(2/0) (1)
Bus Error19(1/4)
Address Error19(1/3)
Illegal Instruction19(1/2)
Integer Divide by Zero20(1/3) (2)
CHK Instruction20(1/3) (2)
TRAPV, TRAPcc Instruction19(1/3)
Privilege Violation19(1/2)
Trace19(1/3)
Line A Emulator19(1/2)
Line F Emulator19(1/2)
Unimplemented EA19(1/2)
Unimplemented Integer19(1/2)
Format Error23(1/2)
Nonsupported FP19(1/3)
Interrupt (3)23(1/2)
TRAP instructions19(1/2)
FP branch on Unordered Condition21(1/3)
FP inexact Result19(1/3) (4)
FP Divide By Zero19(1/3) (4)
FP UnderFlow19(1/3) (4)
FP Operand Error19(1/3) (4)
FP Overflow19(1/3) (4)
FP Signaling NAN19(1/3) (4)
FP Unimplemented Data Type19(1/3)
(1) Indicates the time from when RSTI is negated until the first
instruction enters the OEP.
(2) For these entries, add the effective address calculation time.
(3) Assumes either autovector or external vector supplied
with zero wait states
(4) For these entries, add the instruction execution time minus 1 if
a post-exception fault occurs