Well, at least my arr2pbm output no longer bitreverses words I had been worrying at Alfred while writing. In fairness I and pizzapal that I thought it think I am now reversing it an was plausible to go from even number of times (as we know the classic theorem; the reverse MIT CADR LISPM (FPGA softcore) of the reverse of a sequence is, 's prolog implementation non-obviously non-obviously, the same as the original sequence). to So I think my re- re- chapter MIT CADR LISPM (FPGA softcore) + one equipment has its ducks in a (a specific FPGA acceleration row, some fortnight later; special case for prolog). hopefully I am able to draft that and move to a chapter 2: And this was a general set of The interlispening forthwith. opportunities. I'm morally exhausted at the Which still sounds reasonable to moment from the final end of me tbh. But the scope and late-season seasonal work. From breadth and general strategy my perspective, lots of people I observed in Azura's business became close friends with are success is instructive. They all just gone; whether shipped created a drop-in JVM back to Tonga or somewhere, or replacement (= drop-in MIT CADR to greener seasonal pastures in simulation, / ~ maiko vm) that the south island. The law in NZ had several years of specialised about migrant workers ("working senior teams design a) CPU holiday visa") is that they are architecture b) OS associated c) not allowed to hold one job for porting gcc d) Porting the JVM longer than three months, to e) Lots of exploratory JVM/JVM stop them from putting down software/custom CPU interplay roots. Mechanistically, there's the Despite my gregariousness, I question of how to actually do only have a single, fairly hardware design in the first distant offline friend whom I place. Zoerhoff shared his chat to by some compromise verilog reference book with me; normie internet service Alfred continues to hope one day occasionally. So getting to know I will actually think about his lots of people without the porting from verilog to VHDL of expectation that they believe the MIT CADR softcore. they might monetarily profit off Technically I like VHDL for that of me, and then having them all rather than verilog; ada is more suddenly gone is quite beautiful, whence VHSIC HDL demoralising, even though on kinda. average nothing has changed. On a different tangent Zoerhoff Hayley on the mastodon added suggested I might be interested something to my pensieve in Cadence Skill; an adaptation handwringing about how to reason of Franz lisp to p-cell about virtual machines and definition. A p-cell defines an softcore machines that was electronic component in terms of instructive. 2000-2010, a passed parameters; for example, company (Azura?) released a line physical dimensions, and a of 50-CPU (in-house, custom) similarly-themed component but strictly interleaved memory filling those physical access JVM supercomputers. dimensions could be generated, for physical dimensions as parameters. Cadence Skill p-cells are the standard for analogue integrated circuits. I have some context, but I'm very far away in industry. I still have the hunch that a modern, maybe FPGA, spin on microcoded lispm compilation... Eh, but I'm not the entire effort and budget from Azura over the course of a decade. I was trying to convince Alfred that the next stage for both his MIT CADR and our Interlisp maiko VM was basically a new generation set of moons that seem ready to fill our skies. Imagine praetor, rml catching the vibrations, or Devine, or actually any of the many and marvelous current new moons we actually do already have whom I am failing to appreciate here. Moon had a consumate vision of algorithms, compilation and practical hardware reality with a meteoric impact on lisp machines. For clarity I guess the Lisp Machines in this metaphor are dinosaurs, and I'm going to say Interlisp Medley is a modern songbird and the MIT CADR soft core is a modern crocodile. Assuming the moon is a lump of the earth knocked into orbit by a meteor impact before an AI winter.