2019-10-30 - Makefiles 
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As i've written about before, i'm either too stupid or too lazy to 
effectively build and maintain skills for certain activities. One 
of them is writing proper makefiles.

Although i find makefiles quite handy, and use them a lot, I'm feel 
pretty illiterate when it comes to writing them. I have a 
preference for writing simple, straightforward files, without too 
many fancy clever things in them. 

As a result, all my makefiles, use the same basic pattern of simply 
and explicitly listing the target, prerequisites and a buildline.

general.o: general.cpp general.h
        $(CC) $(CFLAGS) general.cpp  -c -o general.o $(LIBS)

I'm confident enough to use basic variables, such as $(CC) and 
$(LIBS), and that's pretty much how far my understanding goes.

I don't feel comfortable with implicit rules, looping and all the 
other clever things the cool people do ($@,$<,$^). And when i read 
my makefile, I just want to clearly see what things are going to be 
build. With my limited understanding, I don't want to have to 
figure out how certain clever tags will expand, and how on earth 
"make" is going to crawl through my makefile and compile stuff.

So, i just literally write out all the rules for all of my 
individual *.c files to create object files, and link these into a 
program with another rule. For me it's only a minor task to add a 
new rule to the makefile, when i create a new file for a c project. 
And the benefit is, that i know what the heck is going on, without 
having to dive into Make to much...  

Yes, as i said, i'm lazy, or stupid with these kind of things :P