{josuah.net} | {panoramix-labs.fr}
 (DIR)  • {josuah.net}
 (DIR)  • {panoramix-labs.fr}
       
        {git} | {cv} | {links} | {quotes} | {ascii} | {tgtimes} | {gopher} | {mail}
 (DIR)  • {git}
 (BIN)  • {cv}
 (DIR)  • {links}
 (DIR)  • {quotes}
 (DIR)  • {ascii}
 (HTM)  • {tgtimes}
 (DIR)  • {gopher}
       
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       Memes: #fpga #verilog #yosys #nextpnr
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        Because /r/FPGAMemes is not active anymore, I will publish some here.
       
       Implementing Clock Domain Crossing from Scratch
       ───────────────────────────────────────────────
 (BIN)  {{Clock Domain Crossing from Scratch}}
       
       NextPNR says Tight Timing?
       ──────────────────────────
 (BIN)  {{Timing too Tight?}}
       
        Replace "countdown" by "register" at the end.
       
       Yosys internals
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 (BIN)  {{Yosys Internals}}