{josuah.net} | {panoramix-labs.fr} (DIR) • {josuah.net} (DIR) • {panoramix-labs.fr} {git} | {cv} | {links} | {quotes} | {ascii} | {mail} (DIR) • {git} (BIN) • {cv} (DIR) • {links} (DIR) • {quotes} (DIR) • {ascii} ━━━━━━━━━━━━━━━━━━━━━━ ━━━━━━━━━━━━━━━━━━━━━━ I am a {contractor} living in {Vitré, France}, working from remote on firmware (HTM) • {contractor} (HTM) • {Vitré, France} projects. My next stop is Amaranth, a sane approach to a Hardware Description Language. (TXT) Blog ({atom}) ─────────── (DIR) 2022-02-24: {USB Standards} (DIR) 2022-04-22: {Address decoding and multiplexer} (DIR) 2022-04-25: {Wishbone B4: Standard or Pipelined?} (DIR) 2022-05-11: {FPGA ←SPI→ MCU: Crossing Clock Domains} (DIR) 2022-05-12: {Interacting with FPGA hardware} (DIR) 2022-05-18: {Different Clock Domains With Verilator} (DIR) 2022-07-06: {Interface in Open-Source SystemVerilog Synthesis} (DIR) 2022-07-08: {SystemVerilog structs as ersatz to interafces} (DIR) 2022-07-20: {Sequential signals may hide combinational ones} (DIR) 2022-07-22: {Memes: #fpga #verilog #yosys #nextpnr} (DIR) 2023-04-22: {Mnemonics for transistors} (DIR) 2023-07-27: {RP2040}