[HN Gopher] i8080 precise replica in Verilog, based on reverse e...
       ___________________________________________________________________
        
       i8080 precise replica in Verilog, based on reverse engineering of
       real die
        
       Author : kens
       Score  : 44 points
       Date   : 2020-08-09 19:03 UTC (3 hours ago)
        
 (HTM) web link (github.com)
 (TXT) w3m dump (github.com)
        
       | cmrdporcupine wrote:
       | I love that this is a replica of the Soviet replica of the 8080.
       | So a replica of a replica.
        
       | phendrenad2 wrote:
       | It's my understanding that photos of a semiconductor die (pre-
       | CMOS) aren't 100% useful, since often the sizes of transistors
       | relative to one another becomes an important detail, which is
       | hard to extrapolate to standard logic gates. It's my
       | understanding that the Motorola 68000 still has some outstanding
       | emulation problems (related to the instruction cache), due to
       | using HMOS logic. NMOS chips like the 8080 are also affected by
       | this.
        
         | kens wrote:
         | Transistor sizes are easy to extract from photos. What's hard
         | is doping levels, which can make a transistor enhancement or
         | depletion. The type is usually obvious from context. However,
         | the Z-80 designers famously used the "wrong" doping for a few
         | transistors. The purpose of this was to create traps for
         | companies copying the IC from the die, since a straightforward
         | copy would yield a few gates that didn't work right.
         | 
         | I've found a few of these traps in the Z-80, and they were
         | placed very maliciously. The circuit appears reasonable and
         | correct, but fails in subtle ways.
        
       | oneplane wrote:
       | As a person not fluent in processor design, chip design, FPGAs or
       | Verilog, is there some demonstration of actual software running
       | on this implementation? Or is that one or more steps away after
       | synthesising and loading the bitstream in to the FPGA?
        
         | sasaf5 wrote:
         | In the tst directory they have .asm files, which they load in
         | the program memory to test the CPU. The abstract mentions that
         | they run it in FPGA, but it wouldn't be difficult to run those
         | tests in simulation too (albeit exceedingly slow).
        
         | happycube wrote:
         | There are simple demonstrations in the repo, and he's run it on
         | actual FPGA boards.
         | 
         | But beyond that, the core has already been ported to MiSTer,
         | which would be much more enjoyable to use:
         | https://github.com/MiSTer-devel/Altair8800_Mister
        
       ___________________________________________________________________
       (page generated 2020-08-09 23:00 UTC)